Simultaneous multithreading (SMT) processors are widely used in high performance computing tasks. However, with the improved performance of the SMT architecture, the utilization of their functional units is significantly increased, straining the power budget of the processor. This increases not only the dynamic power consumption, but also the leakage power consumption due to the increased temperature. In this paper, a comparison of the static and dynamic sleep signal generation techniques for SMT processors is presented. This is conducted under various workloads to assess their effectiveness in leakage power management. Results show that the dynamic approach exhibits a threefold increase in leakage savings, compared with that of the static approach for certain functional units.

Power gating techniques are rapidly gaining popularity assisting the management of leakage power consumption for deep submicrometer microprocessors' functional units. Power gating is based on an input sleep signal to set the functional unit into a low leakage mode. However, power gating techniques in general inherently lack information about the utilization profile of the functional units they manage. This limitation is usually handled either statically by using a fixed length counter that generates the sleep signal when the functional unit is idle for a specified number of cycles or dynamically by changing the number of cycles before the sleep signal is generated depending on the previous history of operation. In this paper, a comparative study between the static and dynamic approaches regarding the power-performance tradeoff will be presented. It will be shown that the dynamic sleep signal generator is capable of tracking the operation of the functional units while achieving accuracies up to 90% compared to an average of 40%-60% for the static sleep signal generator (SSSG). Additionally it saves up to 80% more leakage versus the SSSG. This study is very important in assisting circuit designers choose between both techniques depending on the power gated circuit.

Leakage power is projected to comprise approximately 50% of the processor's power for sub 65 nm technologies. Much of this power is consumed in the processor's functional units. Accordingly, leakage control techniques are employed to reduce leakage in these functional units. Many of these techniques are dynamic and are based on an input sleep signal to initiate a low leakage mode. However, since most of these leakage control techniques are based on circuit level schemes, such techniques inherently lack information about the operational profile of the functional units they manage. This limitation is usually handled statically by using a fixed length counter that generates the sleep signal when the functional unit is idle for a specified number of cycles. In this paper, the limitations of the static sleep signal generation approach are identified, and the use of a dynamic alternative that is capable of adopting the counter length to the running application is proposed. In order to assess the accuracy of the proposed dynamic sleep signal generator, the length of the sleep period following the sleep signal generation is used as a metric to identify the usefulness of utilizing the dynamic approach. Experimental results for the dynamic alternative shows up to 98% accuracy in predicting the length of the standby period compared to an average of 40-60% in the static case, which translates into increased leakage savings. This is achieved while consuming 360 muW of overhead power at 1 GHz

As VLSI technologies scale down, the average die size is expected to remain constant or to slightly increase with each generation. This results in an average increase in the global interconnect lengths. To mitigate their impact, buffer insertion has become the most widely used technique. However, unconstrained buffering is expected to require several hundreds of thousands of global interconnect buffers. This increased number of buffers is destined to adversely impact the chip power consumption. In this paper, an optimal power maze routing and buffer insertion/sizing problem for a two-pin net is formulated, as a shortest paths ranking problem. The pseudopolynomial time bound of the new formulation fits well within the context of the increased number of buffers. In fact, power savings as high as 25% for the 130-nm technology with a 10% sacrifice in delay is achieved. Furthermore, with the advent of dual threshold technologies, power sensitive applications can substantially benefit from adopting dual threshold buffers. Accordingly, the proposed problem formulation is extended to incorporate the selection of the buffer threshold voltage, where a twofold increase in power savings is observed. During the assessment of the impact of technology scaling using a set of MCNC Benchmarks, an average power saving as high as 35% with a 10% sacrifice in delay is observed. In addition, there is a 10% variation in the power savings when accounting for the process variations.