Abstract The object‐oriented view of the user interface presented here is a model of object responsibilities‐sharing and cooperation for a typical user interface. The model regards the user interface as a three‐layer architecture, with the application contributing to one of the layers called the application exposure, The model seeks to promote user interface software reuse by coupling the user interface and the application with well‐defined message protocols, by properly allocating user interfacefunctions to the layers so as to reduce and discipline their dependencies, and byfactoring complex abstractions into reusable secondary components.

A performance-driven global router for custom VLSI chip design, with the objective of maximizing the minimum delay slack, is presented. Resistances and capacitances of interconnections, input gate capacitances, and output driver resistance are used to approximate the interconnection delays during the routing. The router incrementally updates the delay at each sink pin of the signal obtained from the previous step during the routing. The maximum allowable delay at each sink pin (from a timing analyzer) along with the computer interconnection delays is used to guide the search process for the maximum-delay-slack route. It is shown that when the interconnection resistance is considered, minimizing the total net length is not always equivalent to minimizing the delay for a multiterminal net. The algorithm is experimentally shown to produce global routes achieving the objectives.>

A timing-driven global router is presented for custom chip design, whose objective is maximizing the minimum delay slack. Resistances and capacitances of interconnections, input gate capacitances and output driver resistance are used to approximate the interconnection delays during the routing. The router incrementally updates the delay at each sink pin of the signal obtained from the previous step during the routing. The maximum allowable delay at each sink pin (from a timing analyzer) along with the computed interconnection delays is used to guide the search process for the maximum-delay-slack route. It is shown that when the interconnection resistance is comparable to the output-driver resistance, minimizing the total net length is not always equivalent to minimizing the delay for a multiterminal net. The algorithm presented is experimentally shown to produce global routes achieving the objective.>

Abstract In the past few years we have seen the acceptance of standards for both two and three dimensional computer graphics. Also during this time, the workstation community has converged on a common windowing system. This paper discusses the problems encountered in implementing graphics standards such as GKS and PHIGS PLUS within the X Window System environment.

A procedure for path-delay constrained initial placement during chip floorplanning is presented which directly incorporates timing and geometrical constraints into the process. The problem is modeled and mathematically formulated as a constrained non-linear programming problem which is systematically divided and solved in three steps: timing minimization with module overlap, module separation and timing minimization without module overlap. To save computation time, two techniques for eliminating non-logical and noncritical paths are used to reduce the number of paths considered during the optimization. Experimental results show that the placement results satisfy all given timing and geometrical constraints, and have good total normalized wire delays.

This paper describes a switchbox-type router for custom VLSI module generation as performed by a module planner. A module is decomposed into abstract cells consisting of global routes and Boolean functional specifications. Each abstract cell is given to a cell synthesizer which generates the circuit layout and through-the-cell routing. Abstract routing for a module planner is in some sense similar to switchbox routing to the degree that all of the routes are generated internally within a rectangular boundary (routes are coming from four sides). The principle difference with respect to standard switchbox routing is at the geometric level, where a cell synthesizer generates the routing conduction layers along with circuit devices for each abstract cell within this rectangular region. The aspects of this paper which are thought to be novel contributions are 1) a relative pin assignment algorithm for the abstract cells; 2) a global routing penalty function which not only considers previous routes, but also considers gate complexity within the cells; 3) an efficient optimization algorithm for minimizing the number of tracks running through the module.

In this paper, a new path selection heuristic search algorithm is proposed for connecting two components of vertices. A novel feature of the algorithm is that the active terminals (vertices in the net which are not yet connected) are modeled as magnets during the path searching process. The heuristic search algorithm is applied to two commonly used multi-terminal net tree connection algorithms. Experimental results show that the new path selection heuristic search algorithm is better than the other algorithms which do not consider the active terminals.

High-speed hardware function generation using table look-up in ROM and high-speed multiplication is considered. The reduced interval of interest, [a, b], is split into several large partitions. Within each large partition the functionf(x) is evaluated by piecewise polynomials of the same low degree whose coefficients are stored in ROM. Four basic architectures for such a scheme are considered. A nonlinear programming problem is solved for determining the optimal partitioning of the interval [a, b]. The objective function is the average number of multiplications, which takes into account the probability distribution r(x) = 1/(x ln β), for the mantissas of normalized floating-point numbers where β is the radix of the number system. The constraint is the available number of ROM words. The particular case of f(x) = 1/x and β = 2 is considered in detail and results are presented including an estimate of the number of ROM units required.

This paper discusses a compact, fast, parallel multiplication scheme of the generation-reduction type using generalized Dadda-type pseudoadders for reduction and m X m multipliers for generation. The implications of present and future LSI are considered, a partitioning algorithm is presented, and the results obtained for a 24 X 24-bit implementation are discussed.