EDBT 2026 Demo / reviewers in the wild / expert
Silvia Ercolani
dblp:75/4839
· DBLP profile ↗
4ranked-venue papers
3as first author
0since 2021 · last 1992
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 97% Reconfigurable computing and FPGAs · 3% | |
| Theoretical computer science
1 paper |
Coding theory · 100% |
Topics — the 8 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.0 | 2 | 1992 | Testability measures in pseudorandom testing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 Aliasing in signature analysis testing with multiple input shift registers · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990 |
Electronic design automation › hardware verification and test › fault detection
fault detection probability |
0.0 | 1 | 1992 | Testability measures in pseudorandom testing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Electronic design automation › hardware verification and test › random testing
pseudorandom testing |
0.0 | 1 | 1992 | Testability measures in pseudorandom testing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Electronic design automation › hardware verification and test
testability analysis |
0.0 | 1 | 1992 | Testability measures in pseudorandom testing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1991 | Technology Mapping for Electrically Programmable Gate Arrays · DAC 1991 |
Electronic design automation › logic synthesis
technology mapping |
0.0 | 1 | 1991 | Technology Mapping for Electrically Programmable Gate Arrays · DAC 1991 |
Electronic design automation › hardware verification and test › test response compaction
aliasing probability |
0.0 | 1 | 1990 | Aliasing in signature analysis testing with multiple input shift registers · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990 |
Electronic design automation › hardware verification and test › test response compaction
signature analysis |
0.0 | 1 | 1990 | Aliasing in signature analysis testing with multiple input shift registers · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1990 |
Methods — techniques the papers use, named apart from their topics
signature analysis · 0.0markov process · 0.0signal correlation analysis · 0.0fan-out reconvergence analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1992 | Testability measures in pseudorandom testingabstractThe authors present two methods for computing the fault detection probabilities in combinational networks. The methods provide a deeper insight into the effects of signal correlations caused by multiple fan-out reconvergencies and can be used in testability analysis to predict the fault coverage of pseudorandom patterns. The performances of these algorithms have been tested on significant benchmarks and compare favorably with those of previous procedures.> Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 1991 | Technology Mapping for Electrically Programmable Gate ArraysabstractWe describe a new approach for technology mapping of electri- Silvia Ercolani, Giovanni De Micheli |
DAC | 1 |
| 1990 | Aliasing in signature analysis testing with multiple input shift registersabstractAn investigation of the properties of multiple input shift registers for signature analysis is presented. The assumption of independent errors at the register inputs has been used to model the register behavior as a Markov process whose equations have been solved to obtain the exact dependence of aliasing probabilities as a function of test length, input error probabilities, and feedback structure. Some unique featured of maximum-length registers are proven. Accurate simplified expressions of aliasing probability are derived for use as tools in the evaluation of the coverage.> Maurizio Damiani, Piero Olivo, Michele Favalli, Silvia Ercolani, Bruno Riccò |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 4 |
| 1989 | Improved testability evaluations in combinational logic networksabstractTwo methods for the calculation of fault detection probabilities in combinational networks are presented. These methods provide a better accuracy than existing algorithms and a deeper insight into the effects of first order correlations to multiple fan-out reconvergencies. These techniques have been applied to standard benchmarks as well as to a few commercial circuits and have shown to provide a significant improvement compared with existing methods with minimal drawbacks in terms of required computing resources.> Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò |
ICCD | 1 |