The strong consistency and stateful workflow are seen as the major factors for limiting parallel I/O performance because of the need for locking and state management. While the POSIX-based I/O model dominates modern HPC storage infrastructure, emerging object storage technology can potentially improve I/O performance by eliminating these bottlenecks. Despite a wide deployment on the cloud, its adoption in HPC remains low. We argue one reason is the lack of a suitable programming interface for parallel I/O in scientific applications. In this work, we introduce NoaSci, a Numerical Object Array library for scientific applications. NoaSci supports different data formats (e.g. HDF5, binary), and focuses on supporting nodelocal burst buffers and object stores. We demonstrate for the first time how scientific applications can perform parallel I/O on Seagate’s Motr object store through NoaSci. We evaluate NoaSci’s preliminary performance using the iPIC3D space weather application and position against existing I/O methods.

SAGE (Percipient StorAGe for Exascale Data Centric Computing) is a European Commission funded project towards the era of Exascale computing. Its goal is to design and implement a Big Data/Extreme Computing (BDEC) capable infrastructure with associated software stack. The SAGE system follows a storage centric approach as it is capable of storing and processing large data volumes at the Exascale regime.

Burst error correcting codes, such as fire codes, have traditionally been decoded using linear feedback shift registers (LFSR). However, such sequential decoding schemes are not suitable for modern ultra high-speed channels that demand high-speed parallel decoding employing only combinational logic circuitry. This work proposes a parallel decoding method for cyclic burst error correcting codes. Under this method, a binary companion matrix T defines the entire decoding process. Hence, the decoding method can be implemented using only combinational logic.

Correcting multiple random bit errors that corrupt a single DRAM chip becomes very important in certain applications, such as semiconductor memories used in computer and communication systems, mobile systems, aircraft, and satellites. This is because, in these applications, the presence of strong electromagnetic waves in the environment or the bombardment of an energetic particle on a DRAM chip is highly likely to upset more than just one bit stored in that chip. On the other hand, entire chip failures are often presumed to be less likely events and, in most applications, detection of errors caused by single chip failures are preferred to correction due to check bit length considerations. Under this situation, codes capable of correcting random multiple bit errors that are confined to a single chip output and simultaneously detecting errors caused by single chip failures are attractive for application in high speed memory systems. This paper proposes a class of codes called Single t/b-error Correcting-Single b-bit byte Error Detecting (S/sub t/b/EC-S/sub b/ED) codes which have the capability of correcting random t-bit errors occurring within a single b-bit byte and simultaneously indicating single b-bit byte errors. For the practical case where the chip data output is 8 bits, i.e., b = 8, the S/sub 3/8/EC-S/sub 8/ED code proposed in this paper, for example, requires only 12 check bits at information length 64 bits. Furthermore, this S/sub 3/8/EC-S/sub 8/ED code is capable of correcting errors caused by single subarray data faults, i.e., single 4-bit byte errors, as well. This paper also shows that perfect S/sub (b-t)/b/EC-S/sub b/ED codes, i.e., perfect S/sub t/b/EC-S/sub b/ED codes for the case where t = b - 1, do exist and provides a theorem to construct these codes.

Recent high density wide I/O DRAM chips are highly vulnerable to multiple random bit errors. Therefore, correcting multiple random bit errors that corrupt a single DRAM chip becomes very important in certain applications, such as semiconductor memories used in computer and communication systems, mobile systems, aircraft and satellites. This is because, in these applications, the presence of strong electromagnetic waves in the environment or the bombardment of an energetic particle on a DRAM chip is likely to upset more than just one bit stored in that chip. Under this situation, codes capable of correcting random multiple bit errors that are confined to a single DRAM chip output are suitable for application in high speed semiconductor memory systems. This paper proposes a class of codes called single t/b-error correcting (S/sub t/b/EC) codes which are capable of correcting random t-bit errors occurring within a single b-bit byte. For the case where the chip data output is 16 bits, i.e., b = 16, the S/sub 3/16/EC code proposed in this paper requires only 16 check bits, that is, only one chip is required for check bits at practical information lengths such as 64, 128 and 256 bits. Furthermore, this S/sub 3/16/EC code is capable of detecting more than 95% of all single 16 bit byte errors at information length 64 bits.

This paper proposes a class of systematic codes called single t/B-error correcting - single b-bit byte error correcting - single b-bit block error detecting (S/sub t/B/EC-S/sub b/EC-S/sub B/ED) codes for high speed semiconductor memory systems. The proposed codes correct multiple random t-bit errors occurring within a chip and b-bit byte errors caused by sub-array data faults while simultaneously indicating B-bit block errors caused by complete chip failures.