Meta has traditionally relied on using CPU-based servers for running inference workloads, specifically Deep Learning Recommendation Models (DLRM), but the increasing compute and memory requirements of these models have pushed the company towards using specialized solutions such as GPUs or other hardware accelerators. This paper describes the company's effort in constructing its first silicon specifically designed for recommendation systems; it describes the accelerator architecture and platform design, the software stack for enabling and optimizing PyTorch-based models and provides an initial performance evaluation. With our emerging software stack, we have made significant progress towards reaching the same or higher efficiency as the GPU: We averaged 0.9x perf/W across various DLRMs, and benchmarks show operators such as GEMMs reaching 2x perf/W. Finally, the paper describes the lessons we learned during this journey which can improve the performance and programmability of future generations of architecture.

The architecture and implementation of a MIPS-RISC-based application-specific microprocessor designed specifically for X-Window terminals is described. It consists of a graphics coprocessor integrated with a MIPS-1 (R3000)-compatible CPU core along with system-level functions found in a typical X-Terminal. The design of the graphics coprocessor has been optimized for accelerating low-level graphics operations typical in X-Windows applications. It is implemented as coprocessor 2. A set of coprocessor 2 graphics instructions process pixel data fetched by dedicated DMA channels through a high-bandwidth (64 b) memory interface. The combination of the graphics coprocessor and high-bandwidth memory interface result in a very high performance. The presence of system-level functions on the same die as the CPU and graphics engine make for a very highly integrated processor.>

RISC processors have been widely accepted in the performance driven segments of the reprogrammable computer market such as workstations and file servers. However, these chips, despite their high levels of performance, do not adequately address embedded control applications. A description is given for the macro- and micro-architecture of the LR 33000, a single chip, 50 MHz, RISC processor, which was designed and optimized for embedded control applications while retaining both software compatibility with the MIPS-1 instruction set and a high level of performance. The optimization for embedded control applications was done by focusing on the following goals: minimizing the overall system cost by increasing the level of integration, simplifying the system design, and reducing the power consumption.>