The next-generation 8K ultra-high-definition video format involves an extremely high bit rate, which imposes a high throughput requirement on the entropy decoder component of a video decoder. Context adaptive binary arithmetic coding (CABAC) is the entropy coding tool in the latest video coding standards including H.265/High Efficiency Video Coding and H.264/Advanced Video Coding. Due to critical data dependencies at the algorithm level, a CABAC decoder is difficult to be accelerated by simply leveraging parallelism and pipelining. This letter presents a new very-large-scale integration arithmetic decoder, which is the most critical bottleneck in CABAC decoding. Our design features a variable-clock-cycle-path architecture that exploits the differences in critical path delay and in probability of occurrence between various types of binary symbols (bins). The proposed design also incorporates a novel data-forwarding technique (rLPS forwarding) and a fast path-selection technique (coarse bin type decision), and is enhanced with the capability of processing additional bypass bins. As a result, its maximum throughput achieves 1010 Mbins/s in 90-nm CMOS, when decoding 0.96 bin per clock cycle at a maximum clock rate of 1053 MHz, which outperforms previous works by 19.1%.

This paper presents a measurement-domain intra prediction coding framework that is compatible with compressive sensing (CS) based image sensors. In this framework, we propose a low-complexity intra prediction algorithm that can be directly applied to the measurements captured by the image sensor. Moreover, we propose a structural random 0/1 measurement matrix, embedding the block boundary information that can be extracted from the measurements for intra prediction. Experiment results show that our proposed framework can compress the measurements and increase coding efficiency, with 30% BD-rate reduction compared to the direct output of CS based sensors. This can significantly save both the energy consumption and the bandwidth in communication of wireless camera systems to be massively deployed in the era of IoT.

The paper presents an algorithm to generate a series of deterministic ternary matrices, which are compatible with the new generation of CMOS image sensor (CIS), Compressed Sensing (CS) based CIS (CS-CIS). The proposed matrices are derived from the approximate DCT, hence preserving the energy compaction property as DCT does. With the proposed 2D-zigzag trimming, the limited measurements could compact most of the energy. The experiment result shows that our proposed matrix contributes a significant improvement in image quality and bitrate saving of 5.7 dB BD-PSNR increase on average comparing with the random binary matrix used in the-state-of-art CS-CIS.

No abstract available.

In the past two decades, there has been tremendous progress in video compression technologies. Meanwhile, the use of these technologies, along with the ever-increasing demand for emerging ultra-high-definition applications greatly challenges the design of video codec chips, with the extensive requirements on both memory (DRAM) bandwidth and computation power. Besides, the high data dependencies of video coding algorithms restrict the degree of efficient hardware parallelism and pipelining. This paper describes the techniques to realize high-performance video codec chips. Firstly, we introduce various optimization techniques to solve the DRAM traffic issue. Furthermore, the techniques to reduce the computational complexity and alleviate data dependencies are described. The proposed techniques have been implemented in several ASIC video codecs. Experiments show that the DRAM traffic and DRAM access time are reduced by 80% and 90% respectively. The performance of the video codec chips can achieve [email protected], which is more than 100x better than previous works.

Ultrahigh definition television is becoming increasingly attractive and practical with the doubled compression performance delivered by High Efficiency Video Coding (H.265/HEVC). Meanwhile, implementation of real-time video codecs is challenged by not only the huge throughput and memory bandwidth requirements but also the increased complexity of new algorithms. For motion compensation (MC) that is a known bottleneck in video decoding, the enlarged and diversified prediction unit sizes impose notably higher difficulties in trading off area, power, and memory traffic. This paper presents a very large scale integration implementation of HEVC MC that supports 7680 × 4320@60 frames/s bidirectional prediction. The MC design incorporates a highly efficient cache realized by novel architecture optimizations including distance biased directing mapping, eight-bank memory structure, row-based miss information compression, and mask-based block conflict checking. As a result, the proposed design not only achieves 8× throughput enhancement but also improves hardware efficiency by at least 2.01 times, in comparison with prior arts.

In H.265/high efficiency video coding (HEVC) encoding, rate distortion optimization (RDO) is an important cost function for mode decision and coding structure decision. Despite being near-optimum in terms of coding efficiency, RDO suffers from a high complexity. To address this problem, this paper presents a fast RDO algorithm and its very large scale implementation (VLSI) for both intra- and inter-frame coding. The proposed algorithm employs a quantization-free framework that significantly reduces the complexity for rate and distortion optimization. Meanwhile, it maintains a low degradation of coding efficiency by taking the syntax element organization and probability model of HEVC into consideration. The algorithm is also designed with hardware architecture in mind to support an efficient VLSI implementation. When implemented in the HEVC test model, the proposed algorithm achieves 62% RDO time reduction with 1.85% coding efficiency loss for the “all-intra” configuration. The hardware implementation achieves 1.6 × higher normalized throughput relative to previous works, and it can support a throughput of 8k@30fps (for four fine-processed modes per prediction unit) with 256 k logic gates when working at 200 MHz.

Sample adaptive offset (SAO) is a newly introduced in-loop filtering component in H.265/High Efficiency Video Coding (HEVC). While SAO contributes to a notable coding efficiency improvement, the estimation of SAO parameters dominates the complexity of in-loop filtering in HEVC encoding. This paper presents an efficient VLSI design for SAO estimation. Our design features a dual-clock architecture that processes statistics collection (SC) and parameter decision (PD), the two main functional blocks of SAO estimation, at high- and low-speed clocks, respectively. Such a strategy reduces the overall area by 56% by addressing the heterogeneous data flows of SC and PD. To further improve the area and power efficiency, algorithm-architecture co-optimizations are applied, including a coarse range selection (CRS) and an accumulator bit width reduction (ABR). CRS shrinks the range of fine processed bands for the band offset estimation. ABR further reduces the area by narrowing the accumulators of SC. They together achieve another 25% area reduction. The proposed VLSI design is capable of processing 8k at 120-frames/s encoding. It occupies 51k logic gates, only one-third of the circuit area of the state-of-the-art implementations.

Motion Estimation (ME) is a key performance bottleneck of H.265/HEVC encoding. In implementing ME, a fixed or bounded complexity is often desired for efficient pipelining and parallelism. We present a fixed-complexity mode filtering algorithm to reduce the complexity of fractional ME (FME). Firstly, a layer filtering is applied to select the mode candidates. Secondly, the ratio of integer-fractional ME costs (Rf/i) is defined and the confidence interval of Rf/iis utilized for further mode selection. Finally, an algorithm to fix the complexity is applied. Experimental results show that the FME encoding time is reduced by 83.3% with slightly BD-rate increase.

FRC (frame re-compression) is a kind of widely used technique in reducing the SDRAM (synchronous dynamic random access memory) bandwidth of HEVC video system. However, in previous research works, FRC imposes requirements on accessing pattern and hence its usage are only limited in HEVC video codecs. While in a typical HEVC VLSI video system, there exists many other video IPs with high bandwidth requirements. Therefore, in this article, we propose a new FRC architecture to overcome the limitation and make it applicable to all the video IPs in a HEVC VLSI video system, which raises the overall bandwidth reduction rate of the whole video system. Our proposal has two points: firstly we propose a system internal bus based FRC architecture, which is independent, transparent, and easily connected to all other video IPs. Secondly, we propose a FA (freely access) scheme to remove the requirements on access pattern in previous work. By using this proposal, the bandwidth reduction rate in our VLSI video system model is raised from 92.4% to 69.6%.

Ultra high definition television (UHDTV) imposes extremely high throughput requirement on video encoders based on High Efficiency Video Coding (H.265/HEVC) and Advanced Video Coding (H.264/AVC) standards. Context-adaptive binary arithmetic coding (CABAC) is the entropy coding component of these standards. In very-large-scale integration implementation, CABAC has known difficulties in being effectively pipelined and parallelized, due to the critical bin-to-bin data dependencies in its algorithm. This paper addresses the throughput requirement of CABAC encoding for UHDTV applications. The proposed optimizations including prenormalization, hybrid path coverage and lookahead rLPS to reduce the critical path delay of binary arithmetic encoding (BAE) by exploiting the incompleteness of data dependencies in rLPS updating. Meanwhile, the number of bins BAE delivers per clock cycle is increased by the proposed bypass bin splitting technique. The context modeling and binarization components are also optimized. As a result, our CABAC encoder delivers an average of 4.37 bins per clock cycle. Its maximum clock frequency reaches 420 MHz when synthesized in 90 nm. The corresponding overall throughput is 1836 Mbin/s that is 62.5% higher than the state-of-the-art architecture.

Fractional motion estimation (FME) significantly enhances video compression efficiency, but its high computational complexity also limits the real-time processing capability. In this brief, we present a VLSI implementation of FME design in High Efficiency Video Coding for ultrahigh definition video applications. We first propose a bilinear quarter pixel approximation, together with a search pattern based on it to reduce the complexity of interpolation and fractional search process. Furthermore, a data reuse strategy is exploited to reduce the hardware cost of transform. In addition, using the considered pixel parallelism and dedicated access pattern for memory, we fully pipeline the computation and achieve high hardware utilization. This design has been implemented as a 65-nm CMOS chip and verified. The measured throughput reaches 995 Mpixels/s for 7680 × 4320 30 frames/s at 188 MHz, at least 4.7 times faster than prior arts. The corresponding power dissipation is 198.6 mW, with a power efficiency of 0.2 nJ/pixel. Due to the optimization, our work achieves more than 52% improvement on power efficiency, relative to previous works in H.264.

The first single-chip design that supports real-time H.264/Advanced Video Coding decoding of 8k (7680×4320) 60 frames/s is realized. It also supports multiview decoding for up to 32720p views or 161080p views. To significantly improve the throughput and reduce the memory bandwidth requirement, frame-level parallelism is exploited for the proposed design. First, a frame dependency protection scheme enables frame-parallel decoding, by reusing multiple replicas of an existing design. This results in a system throughput of 2 Gpixels/s, at least 3.75 times better than previous chips. Moreover, a reference window synchronization scheme and a 2-level hybrid caching structure are proposed to achieve 44% memory bandwidth reduction of motion compensation, by utilizing frame-level data reuse. The bandwidth reduction results in 22% Dynamic Random-Access Memory power saving of the whole decoder.

This paper presents a high quality H.265/HEVC motion estimation implementation with the cooperation of CPU and GPU. The data dependency from MVP (Motion Vector Predictor) restricts the degree of parallelism on GPU. To overcome the constraint from MVP, we propose to use an estimated MVP on GPU and the accurate MVP to refine the motion vector on CPU. GPU fully utilizes its tremendous parallel computing ability without the restriction from MVP. CPU makes up for the deviation from GPU with a small range refinement. Encoding speed benefits from the high degree of parallelism and compression performance is maintained by the CPU refinement. Experimental result shows that the speedup achieves 2.39 times and 32.77 times in the whole ×265 encoder with CPU SIMD (Single Instruction Multiple Data) on and off, respectively. On the other hand, the quality degradation is negligible with only 0.05% increase of BD-rate.

This paper presents a high-throughput decoder of HEVC context-based adaptive binary arithmetic coding (CABAC). A multi-sub-engine arithmetic decoder (MSE-AD) design is proposed to increase the average number of bins delivered per clock cycle by adaptively processing different patterns of upcoming bins with balanced critical path delay. A syntax element (SE) grouping scheme is proposed to maximize the utilization of MSE-AD under the SE parsing order specified in the standard. We also employ a prediction-based pipeline to alleviate the data hazard problem. The proposed CABAC decoder delivers 2.36 bins per clock cycle and achieves a maximum clock frequency of 258MHz in 90nm technology. The resulting performance is 610 Mbin/s which is enough for H.265/HEVC level 6.1 (8K×4K@60fps) applications.

Motion estimation and motion compensation in HEVC and similar video codecs involve huge memory traffic in storing and loading reference frames. The resulting memory power composes a significant portion of system energy consumption. This paper presents a memory power reduction framework that losslessly compresses and decompresses reference frames on-the-fly. We first present the architecture that supports the random access of frame data compressed in variable ratios. The latest recompression algorithms and the corresponding VLSI implementation are also introduced. The framework has been implemented in several UHDTV ASIC and FPGA codecs. Experiments under HEVC common test conditions show an average memory traffic reduction of near 60%.

This paper presents an efficient VLSI architecture of intra prediction for 8K×4K HEVC decoder. It supports all 35 intra prediction modes and prediction sizes ranging from 4×4 to 64×64. This works proposed a Cyclic SRAM Banks based Parallel Reference Sample Fetching (CSB-PRSF), which guarantees enough reference samples for prediction and reduces the number of registers used for storing reference samples. To guarantee high throughput, 16 pixels are predicted by 4×4 Block Based Pipelining, and dependency between neighboring blocks is eliminated by Hybrid Data Forwarding and Block Reordering. This architecture is synthesized using 90nm technology and the maximum working frequency is 469 MHz, with 72.1K gates area. Running at 397MHz, the architecture can support 4320p@120fps HEVC intra decoding, with full modes and full sizes.

SAO estimation is the process of determining SAO parameters in video encoding. There are two difficulties for VLSI implementation of SAO estimation. The first is that there are huge amount of samples to deal with in statistic collection phase. The other is that the complexity of RDO in parameters determination phase is very high. In this article, a fast SAO estimation algorithm and its corresponding VLSI architecture are proposed. For the first difficulty, we use bitmaps to collect statistic of all the 16 samples in one 4×4 block simultaneously. For the second difficulty, we simplify a series of complicated procedures in HM to balance the complexity and BD-rate performance. Experimental results show that the proposed algorithm maintains the picture quality improvement. The VLSI design based on this algorithm can be implemented by 156.32K gates, 8832 bits SPRAM, 400MHz @ 65nm technology and is capable of 8Kx4K @ 120fps encoding.

This paper presents a motion compensation (MC) architecture for 8K UHDTV HEVC video decoder. UHDTV's high resolution significantly increases throughput and memory traffic. Moreover, HEVC supports new coding tools like various sizes of coding unit ranging from 8 to 64. To solve these problems, we propose three optimization schemes. Firstly, four-bank parallel 2D cache organization is proposed to reduce 61.86% memory traffic and support higher interpolator throughput for HEVC. Secondly, we propose pipelined Write-Through mechanism (WTM) to achieve conflict-free performance. Moreover, WTM scheme contributes to around 50% reduction on both memory area and logic gate. Finally, highly parallel interpolator with proposed cache forms integral structure supporting UHDTV. In 90nm process, our design cost 103.6k logic gates with 12kB cache memory. The proposed architecture can support real-time decoding 7680×4320@30fps at 280MHz.

This paper proposes a hybrid message-passing decoding algorithm which consumes very low computational complexity, while achieving competitive error performance compared with conventional min-max algorithm. Simulation result on a (255,175) cyclic code shows that this algorithm obtains at least 0.5dB coding gain over other state-of-the-art low-complexity non-binary LDPC (NB-LDPC) decoding algorithms. Based on this algorithm, a partial-parallel decoder architecture is implemented for cyclic NB-LDPC codes, where the variable node units are redesigned and the routing network is optimized for the proposed algorithm. Synthesis results demonstrate that about 24.3% gates and 12% memories can be saved over previous works.

This paper presents a new VLSI architecture for HEVC inverse discrete cosine transform (TDCT). Compared to prior arts, this work reduces hardware cost by: reducing computational logic of 1-D IDCTs with a reordered parallel-in serial-out (RPISO) scheme that shares the inputs of the butterfly structure; and reducing the area of the transpose buffer with a cyclic memory organization that achieves 100% I/O utilization of the SRAMs. In the implementation of a unified 4/8/16/32-point IDCT, the proposed schemes demonstrate 35% and 62% reduction of logic and memory costs, respectively. The IDCT implementation can support real-time decoding of 4K×2K 60fps video with a total hardware cost of 357,250um2on 2-D IDCT and 80,988um2on transpose memory in 90nm process.

In this paper, a motion estimation processor (MEP) with 3D stacked memory architecture is proposed to 1) reduce the memory and core power consumption; 2) provide higher bandwidth. Firstly, a memory die is designed and staked with MEP die. By adding face-to-face (F2F) pad and through silicon vias (TSV) definitions, 2D electronic design automation (EDA) tools are extended to support the proposed 3D stacking architecture. Moreover, a novel memory controller is applied to control the data transmission and the timing between memory die and MEP die. Finally, 3D physical design is completed for the whole system including TSV/F2F placement, floor plan optimization, power network generation, etc. Comparing with 2D technology, the number of IO pins is reduced by 77%. After optimizing the floor plan of the MEP die and memory die, the routing wire length is reduced by 13.4% and 50% respectively. The simulation results show that the max bandwidth is more than 14GB/s and whole design can support real-time 720p@60fps encoding at 8MHz with less than 65mW, which is only one sixth of the state-of-the-art MEP.

Video encoders and decoders for HEVC-like compression standards require huge external memory bandwidth, which occupies a significant portion of the codec power consumption. To reduce the memory bandwidth, this paper presents a new lossless reference frame recompression algorithm along with a high-throughput hardware architecture. Firstly, hybrid spatial -domain prediction is proposed to combine the merits of DPCM scanning and averaging. The prediction is then enhanced with multiple modes to accommodate various image characteristics. Finally, efficient residual regrouping based on semi-fixed-length (SFL) coding is used to improve the compression performance. Compared to no compression, the proposed scheme can reduce data traffic by an average of 57.6% with no image quality degradation. The average compression ratio is 2.49, an improvement of at least 12.2-13.2%, relative to the state-of-the-art algorithms. By applying a reordered two-step architecture and the two optimizations, residual reuse and simplified coding mode decision, the hardware cost is similar to that of previous reference frame recompression architectures. The computational complexity increase caused by multi-mode prediction affects the HW cost slightly. This work can be implemented with 45.1 k gates for the compressor and 34.5 k gates for the decompressor at 300 MHz, enough to support a 3840 ×2160@60fps video encoder and decoder.

This paper presents an H.264/AVC intra-prediction design for ultrahigh definition (ultra-HD) video. Due to the huge throughput requirements of ultra-HD, design challenges such as complexity and data dependency, which currently exist for lower resolutions, become even more critical. To solve these problems, we first propose an interlaced block reordering scheme together with a preliminary mode decision (PMD) strategy to resolve the data dependency between intra mode decision and reconstruction. In the meantime, hardware cost is reduced by PMD. We also propose a probability-based reconstruction scheme to solve the problem of long pipeline latency. In addition, hardware reuse strategies including a shared fine decision module and processing element-reusable prediction generator, are applied to further optimize the design. As a result, the hardware complexity is reduced by 77% in terms of area and frequency, and it takes an average of 33 cycles to process a macroblock. The implementation result demonstrates that our design can support up to the specification of 7680 × 4320p 60 f/s when running at 273 MHz. The design is implemented with 451.5 k gates in 65-nm CMOS.

An LDPC decoder in 65nm CMOS targeting WPAN (IEEE 802.15.3c) is presented with measurement results. A modified-PCM based message permutation strategy with compatible data flow is proposed to solve the network problem raised by high parallelism LDPC decoding. Compared to the state-of-art, decoder chip achieves 17.7%, 33.5% and 49% improvements in chip density, gate count and energy efficiency, respectively.

An H.264/AVC intra-frame video encoder is implemented in 65nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991Mpixels/s for 7680×4320p 60fps video, 9.4x to 32x faster than previous designs. The encoder also incorporates a 1.41Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption is achieved by the high parallelism and hardware efficiency of this design. 1080p 30fps encoding dissipates only 2mW at 0.8V and 9MHz.

A combined hole-filling approach with spatial and temporal prediction is presented in this paper. Depth image-based rendering (DIBR) is generally used to synthesize virtual view images in free viewpoint television (FTV) and three-dimensional (3-D) video. Limited original camera views and depth maps are used to generate the additional virtual views in the synthesizing process. One of the main problems in DIBR is that there are some regions are occluded by the foreground objects in the original views, and they will be some holes in the generated additional virtual views, especially for the view extrapolation cases. Therefore, the proposed algorithm is introduced and it can be used to fill the holes which caused by disocclusion regions and inaccurate depth values. The proposed algorithm combines the spatial and temporal prediction, and the performance is much better and more stable than the previous work. The experimental results show that the proposed method can improve the quality of the virtual views a lot compared with the previous work. The improvement is not only obvious in the objective comparison, but also in the subjective comparison.

This paper presents a high-performance context adaptive binary arithmetic coding (CABAC) architecture for the next-generation UHDTV applications. Its maximum throughput has been enhanced by 31%~34% with the proposed pre-normalization (prenorm.), hybrid path coverage (HPC), bypass bin splitting (BPBS) and state dual-transition (SDT) schemes. Both the HEVC and H.264/AVC formats can be supported with our architecture by applying a dualstandard binarization design. The proposed CABAC architecture has been silicon proven in a 65nm video encoder chip. It delivers 4.27~4.40 bins/cycle with synthesized and measured clock rates of 401.5MHz and 330MHz, respectively. Therefore a high performance of 1.452Gbin/s is achieved for real-time UHDTV encoding.

The up-coming video compression standard, high efficiency video coding (HEVC), reduces 50% bit rates in encoding video sequences with same picture quality compared to H.264/AVC. In the in-loop filter (LF) part of HEVC, sample adaptive offset (SAO) is newly added and de-blocking filter (DBF) has been changed a lot. Thus how to construct a high speed and low cost VLSI architecture for HEVC SAO and de-blocking filter is a challenge. In this article, we propose a HEVC LF architecture composed of fully utilized de-blocking filter and SAO. Block based SAO and DBF are employed in this architecture to achieve seamless pipeline between them. The implementation results show that it can be synthesized to 240MHz with 65nm technology. Thus this solution can process 3.84G pixels/s and support 4320p(7680×4320)@120fps decoding.

In recent years, local pattern based features have attracted increasing interest in object detection and recognition systems. Local Binary Pattern (LBP) feature is widely used in texture classification and face detection. But the original definition of LBP is not suitable for human detection. In this paper, we propose a novel feature set named gradient local binary patterns (GLBP), Original GLBP and Improved GLBP, for human detection. Experiments are performed on INRIA dataset, which shows the proposal GLBP feature is more discriminative than histogram of orientated gradient (HOG), histogram of template (HOT) and Semantic Local Binary Patterns (S-LBP), under the same training method. In our experiments, the window size is fixed. That means the performance can be improved by boosting and cascade methods. And the computation of GLBP feature is parallel, which make it easy for hardware acceleration. These factors make GLBP feature possible for real-time human detection.

A multilayer routing system usually adopts multiple interconnect configuration with different wire sizes and thicknesses. Since thicker layers of metal lead to fatter wires with smaller resistance, the layer assignment of nets has a large impact on the interconnect delay. However, such layer dependent characteristics have been ignored by most of the state-of-the-art academic layer assignment methods. To remedy this deficiency, this work studies a more effective layer assignment problem under such multi-tier interconnect structure, which arises during 3D global routing and focuses on minimizing both delays and via count. This work presents a two-stage algorithm to solve the problem, which first minimizes the total delay and via count simultaneously by dynamic programming and negotiation technique, and then further minimizes the maximum delay carefully while not increasing the via count. The experimental results on ICCAD09 benchmarks show that the proposed algorithm can significantly reduce the total delay and maximum delay while still keeping roughly the same via count, compared with the state-of-the-art via count minimization layer assignment method NVM.

In the high efficiency video coding (HEVC), motion estimation (ME) is an essential process for inter prediction. Compared to integer ME (IME), fractional ME (FME) occupies much more encoding time in the fast search case. To reduce the computational complexity of FME, we propose a fast algorithm based on mode filtering. In the proposal, according to results of IME and neighboring largest coding units (LCU), 1 or 2 levels are selected from the original 4-level quad-tree structure, and only the selected levels will process FME. Specifically, quad-tree separation is adopted to remove the interdependence between IME and FME. Experiments on a wide range of video sequences show that the proposed algorithm can reduce up to 42.9% and an average of 33.4% total encoding time for HEVC with little loss in PSNR and rate.

In this paper, a feature named multi-scale bidirectional local template patterns (MBLTP) is proposed for human detection. As an extension of bidirectional local template patterns (BLTP), MBLTP not only integrates the textural and gradient information according to the four predefined templates but also calculates information for additional feature vectors by adjusting the scale of the training samples. These additional feature vectors contain multi-scale information on the samples, which can make the feature more discriminative than its original form. Experimental results for an INRIA dataset show that the detection rate of our proposed MBLTP feature outperforms those of other features such as the multi-level histogram of orientated gradient (multi-level HOG), multi scale block histogram of template (MB-HOT), and HOG-LBP. Moreover, in order to make our feature meet real-time requirements, an implementation based on a graphic process unit (GPU) is adopted to accelerate the calculation.

In this paper, we propose a moving object tracking method in the compressed domain. Because video data are large in size, it is usually compressed by H.264/AVC or MPEG for storage or transmission. Most image processing systems track targets in the pixel domain after decoding compressed data. Objects in video data are tracked based on their color and luminance information in the pixel domain. However, tracking methods in the pixel domain have higher computational complexity than in the compressed domain. We propose a method that directly employs moving object tracking in the compressed domain without a decoding process. Tracking algorithms in the compressed domain are usually based on motion information, or motion vectors. However, motion vectors are not generated when objects stop moving, and their accuracy is low. To overcome these problems, we propose a method that uses motion vectors and other information in macroblocks to track moving objects in a compressed H.264/AVC video stream. The proposed method can reduce computational complexity compared to a pixel domain algorithm. In addition, experimental results show that tracking accuracy is improved by the proposed method. Therefore, this method can be effectively used for video surveillance systems.

We considered the one-sided single-detour untangling twisted nets problem for printed circuit board bus routing. A previous optimal dynamic programming based O(n3) algorithm was proposed in a previous work, where n is the number of nets. In this paper, we propose an optimal O(n) untangling algorithm without considering capacity, and this algorithm is further modified to consider capacity. Experimental results show that our algorithms runs much faster than the previous work due to its low time complexity.

In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.

In the latest draft video compression standard, HEVC, a new 8-tap MC interpolation filter is adopted. For this component, we propose an efficient VLSI design which is composed of a reconfigurable filter, an optimized pipeline engine organization, and a filter reuse scheme. This results in 30% area saving from a non-optimized design. The proposed implementation supports a maximal throughput of QFHD@60fps. Our results also demonstrate the implementation cost of a well optimized HEVC interpolation component can be comparable to that of H.264, despite of the enhanced coding performance.

Bidirectional motion estimation significantly enhances video coding efficiency, but its huge complexity is also a critical problem for implementation. This paper presents an interlaced asymmetric search range assignment (IASRA) algorithm. By applying a large and a small search ranges to two reference directions and switching the assignment of these two search ranges once per macroblock, total complexity for bidirectional motion estimation can be reduced by near half with slight coding efficiency drop. IASRA also has the flexibility to be combined with existing fast algorithms and architectures for further complexity saving. We demonstrate this feature by combining IASRA with the state-of-the-art IMNPDR and PMRME architectures, which results in 33% to 42% complexity reduction with less than 1% bit rate increase.

HEVC achieves a better coding efficiency relative to prior standards, but also involves increased complexity. For intra prediction, complexity is especially intensive due to a highly flexible coding unit structure and a large number of prediction modes. This paper presents a low-complexity intra prediction algorithm for HEVC. A fast preprocessing stage based on a simplified cost model is proposed. Based on its results, a level filtering scheme reduces the number of prediction unit levels that requires fine processing from 5 to 2. To supply level filtering decision with appropriate thresholds, a fast training method is also designed. A mode filtering scheme further reduces the maximum number of angular modes to be evaluated from 34 to 9. Complexity reduction from HM 3.0 is over 50% and stable for various sequences, which makes the proposed algorithm suitable for real-time applications. The corresponding bit rate increase is lower than 2.5%.

In this paper, we propose a novel high-speed stereo matching algorithm using pixel classification and reliable disparity propagation. While the research on stereo matching has such a long history and many state-of-art strategies have been introduced in recent years, the contradiction between the quality and the time consumes has not yet been solved. Our stereo method tackles this problem with two key contributions. First, we classify all the pixels into two categories: consecutive pixels and isolated pixels. When we perform matching cost aggregation, different supports are constructed for different types of pixels. For a consecutive pixel, an orthogonal local support skeleton is adaptively constructed. For an isolated pixel, we build an adaptive binary window. Second, we simultaneously conduct the matching cost aggregation and reliability detection. Once a reliable disparity is found, we propagate it to the whole support region. Experiments show that this algorithm can significantly reduce the computational complexity and ensure the accuracy of the result at the same time.

Weather such as rain and snow cause difficulties in processing the videos captured. Since the appearance of rain drops can affect the performance of human tracking and reduce the efficiency of video compression, detection and removal of rain is a challenging problem in outdoor surveillance systems. In this paper, we propose a new algorithm for rain detection, which is based on joint spatial and wavelet domain features. This approach is robust to the videos with moving objects in the rain. Experimental results demonstrated its better performance in comparison with the existing approaches in the subjective quality.

Because of the limitation in the imaging system, videos captured by mobile devices are usually noisy. In this paper, a noise robust fast video encoding scheme is proposed based on Retinex theory. The reflectance image is estimated in a co-analysis module by Retinex theory, within which the content similarity is detected to conduct the encoding process. Experimental results demonstrate that the proposed encoding scheme provides an average of 18.42 times higher encoding speed relative to the existing approaches without sacrificing the subjective quality.

The quadtree based picture partition scheme in HEVC contributes to significant coding efficiency improvement, especially for high resolution videos. But encoding complexity also increases dramatically. This paper brings forward a two-stage prediction unit size decision algorithm to speed up the original intra coding in HEVC. In the pre-stage, texture complexity of down-sampled largest coding unit (LCU) and its four sub-blocks are analyzed according to video content, to filter out unnecessary prediction units for both the LCU and its sub-blocks. Secondly, during intra coding, prediction unit sizes of encoded neighboring blocks are utilized to skip small prediction unit candidates for current block. Experimental results show that proposed algorithm can speed up original HEVC intra coding by a factor of up to 73.7% and by averagely 44.91% for 4k×2k video sequences. Meanwhile, the peak signal-to-noise ratio degradation is less than 0.04dB and bit-rate stays almost the same compared with that of original HEVC intra coding.

Occlusions significantly affect the result during human tracking. This paper proposes a novel occlusion detection and handling algorithm which is mainly based on the KLT (Kanade-Lucas-Tomasi) method. Instead of using KLT as a tracker, we apply it for occlusion detection to enhance tracking stability. In this paper, a combinational method of particle filter tracking and occlusion detection is proposed. Depending on the detection result, our method makes decisions that whether to update the appearance model and use the occlusion handling strategy. Our occlusion detector associates color information, KLT feature tracker and directions of feature points. Additional, the occlusion handling strategy is based on the information from detection. Moreover, the algorithm also can solve the drift problem. Experimental results on famous datasets prove that our method has better performance and robustness on occlusion detection and handling.

Foreground extraction and moving object detection are often used in human tracking systems. However those methods are not able to produce accurate results when objects are too close or when occlusions happen since the result is generally a single big blob which contains all the different objects. In this paper we propose a novel and efficient moving object detection enhancement method. Indeed, by using the results of the previous iteration tracking we are able to keep a correct number of moving objects by removing useless blobs and by splitting those which contain more than one tracker. The method can also speed up the tracking by creating a link between a tracker and a blob to avoid unnecessary processing in some situations.

With the popularity of mobile devices with embedded video cameras, real-time video encoding on hand-held devices becomes increasingly popular. Reducing the power consumption during real-time video encoding to suspend the battery life with the same encoding performance is very important to improve the quality of service. Although some workload estimation techniques have been developed for video decoding to reduce power consumption for video playback applications, they present inefficiency in being transferred to video encoding directly because the compressed information cannot be retrieved before encoding and the future input video content is often nondeterministic. In this paper, a workload estimation scheme targeting video encoding applications is proposed. Based on the definition of video encoding workload and the analysis of the features, a Hilbert transform-based workload estimation model is proposed to predict the overall variation trend in the encoding workload to overcome the workload fluctuations and the nondeterministic content variations, e.g., burst motion. The effectiveness of the proposed algorithm is demonstrated on two H.264/AVC encoders on PC and an embedded platform by encoding different video contents at different bit-rates. The proposed algorithm provides a negligible deadline missing ratio around 4.8%, which is much lower than the previous solutions, together with platform and content robustness. Compared with the previous solutions, the proposed algorithm provides up to 61.69% power reduction under the same performance constraint.

In this paper, we present a hardware-efficient fast algorithm with a lossless frame recompression scheme and early-level termination strategy for large search range (SR) motion estimation (ME) utilized in beyond high-definition video encoder. To achieve high ME quality for hierarchical motion search, we propose an advanced hierarchical ME scheme which processes the multiresolution motion search with an efficient refining stage. This enables high data and hardware reuse for much lower bandwidth and memory cost, while achieving higher ME quality than previous works. In addition, a lossless frame recompression scheme based on this ME algorithm is presented to further reduce bandwidth. A hierarchical memory organization as well as a leveling two-step data fetching strategy is applied to meet constraint of random access for hierarchical motion search structure. Also, the leveling compression strategy by allowing a lower level to refer to a higher one for compression is proposed to efficiently reduce the bandwidth. Furthermore, an early-level termination method suitable for hierarchical ME structure is also applied. This method terminates high-level redundant motion searches by establishing thresholds based on current block mode and motion search level; it also applies the early refinement termination in order to avoid unnecessary refinement for high levels. Experimental results show that the total scheme has a much lower bit rate increasing compared with previous works especially for high motion sequences, while achieving a considerable saving of memory and bandwidth cost for large SR of [-128,127].

Low power design has become one of the most significant requirements when CMOS technology entered the nanometer era. Therefore, timing budget is often performed to slow down as many components as possible so that timing slacks can be applied to reduce the power consumption while maintaining the performance of the whole design. Retiming is a procedure that involves the relocation of flip-flops (FFs) across logic gates to achieve faster clocking speed. In this paper we show that the retiming and slack budgeting problem can be formulated to a convex cost dual network flow problem. Both the theoretical analysis and experimental results show the efficiency of our approach which can not only reduce power consumption by 8.9%, but also speedup previous work by 500 times.

As technology advances, 3-D stacking of silicon layers is emerging as a promising approach to address the integration challenges faced by current System-on-Chips (SoCs). Designing efficient Network- on-Chips (NoCs) is necessary to handle the 3-D interconnect complexity. In this paper, we present a four-stage synthesis approach to determine the power-performance efficient 3-D NoC topology for the application. First, we propose an algorithm to explore optimal clustering of cores during 3-D floorplanning. Then, an Integer Linear Programming (ILP) algorithm is proposed to place switches and network interfaces on the 3-D floorplan. Thirdly, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. Last, a min-cost max-flow based algorithm is proposed for Through-Silicon Via (TSV) assignment to minimize the link power consumption. Experimental results show the effectiveness of the proposed algorithm.

In this paper, a novel approach is proposed to achieve the foreground objects detection in video surveillance system using codebook method. The block-based background model upgrades the pixel-based codebook model to block level which can utilize the dependency and find relationships between neighbouring pixels, thus improving the processing speed and reducing memory during model construction and foreground detection. Moreover, by adding the orientation and magnitude of the block gradient, the codebook model contains not only information of color, but also the texture feature. The texture information can further reduce noises and refine more entire foreground regions. Experimental results prove that our method has better performance compared with the standard codebook and some other former algorithms.

In this paper, new raster scan orders other than the conventional horizontal scan from the top-left corner of the image/slice are proposed to fully exploit content correlation from the regions right to and below the current coding unit. By being applied to each slice/frame adaptively with the conventional one, features influencing the scan order selection are investigated. Different adaptive scan schemes are tested and compared. Up to 3.4% bit-rate reduction can be achieved for Intra coding with limited increase in complexity.

In this paper, a low power parallel surveillance video encoding system based on joint power-speed scheduling is proposed. The relative relationships among the CPU statuses, total power consumption and encoding speed are analyzed and modeled for multi-core processors. Based on the power directional graph and the relative encoding speed model, the working statuses of the cores are controlled jointly adapting to video encoding workload to minimize the total power consumption. It provides more than 20% power reduction compared with the latest existing system without a penalty on the encoding speed.

Through packing the two neighboring views after down-sampling into one frame, frame-compatible format coding allows stereo video to be encoded on the conventional video applications. Using the content similarity which leads to similar prediction between the two packed planes, a fast algorithm is discussed in this paper. The target of the proposed algorithm is to reduce the computational complexity and maintain the compression performance. By operating the candidate predictions solely on the half of a frame (plane_1) according to the encoded half of the frame (plane_0), it introduces an average of 75.7% and 90.4% reduction in planet's computational complexity for Intra and Inter encoding, respectively. The statistic analysis illustrates the prediction correlation due to the content similarity, and contributes to the prediction candidate sets for Intra and Inter coding. In addition, a shift obtaining method integrated in the fast algorithm is also introduced.

Multipath delay profile models for ITS wireless communications are presented. Assuming roadside-to-vehicle communications and vehicle-to-vehicle communications, propagation measurement was carried out using 700MHz spectrum and delay profile models are established based on the measured data. In the paper, the method to extract the delay profile models from the measured data is firstly presented. The established models are presented for LOS and NLOS environments. The simulated transmission performance using the model is also shown assuming RC-006 specifications.

Because of the outstanding contribution in improving compression efficiency, block-based quantization has been widely accepted in state-of-the-art image/video coding standards. However, false contour artifacts are introduced, which result in reducing the fidelity of the decoded image/video especially in terms of subjective quality. In this paper, a block-based decontouring method is proposed to reduce the false contour artifacts in the decoded image/video by automatically dithering its direct current (DC) value according to a composite model established between gradient smoothness and block-edge smoothness. Feature points on the model with the corresponding criteria in suppressing contour artifacts are compared to show a good consistency between the model and the actual processing effects. Discrete cosine transform (DCT)-based block level contour artifacts detection mechanism ensures the blocks within the texture region are not affected by the DC dithering. Both the implementation method and the algorithm complexity are analyzed to present the feasibility in integrating the proposed method into an existing video decoder on an embedded platform or system-on-chip (SoC). Experimental results demonstrate the effectiveness of the proposed method both in terms of subjective quality and processing complexity in comparison with the previous methods.

Permutation network plays an important role in the reconfigurable QC-LDPC decoder for most modern wireless communication systems with multiple code rates and various code lengths. In this paper, we propose the variation Banyan network (VBN) based permutation network architecture for the reconfigurable QC-LDPC decoders and give the control signal generating algorithm for cyclic shift. Through introducing the bypass network, we put forward the nonblocking scheme for any input number and shift number. In addition, the optimized VBN is proposed for WiMAX and WiFi standard, which can shift at most 4 groups of input data, and greatly reduce the hardware complexity. The synthesis results using the 90 nm technology demonstrate that the proposed permutation network can be implemented with the gate count of 18.3 k and the frequency of 600 MHz.

Network-on-chip (NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving.

As a global interconnection, bus is critical for chip performance in deep submicron technology. Reducing bus routing vias will facilitate the lithography and give bus routing a higher yield and also a higher performance. In this paper, we present a floorplan revising method to minimize the number of reducible routing vias with a controllable loss on the chip area and wirelength. Therefore, it is easy to make a proper tradeoff between via reduction and revising loss. Experiments show that our method reaches a 96.2% and 93.5% reduction of routing vias, which is close to 100% and runs fast. Besides, our revising is friendly to all third-party floorplanners, which can be applied to any existing floorplans to reduce vias. It is also scalable to larger benchmarks.

We revisit voltage partitioning problem when the mapped voltages of functional units are predetermined. If energy consumption is estimated by formulation E=CV2,a published work claimed this problem was NP-hard. We clarify that it is polynomial solvable, then propose an optimal algorithm, its time complexity is O(nk+k2d) which is best so far, where n, k, and d are respectively the numbers of functional units, available supply voltages, and voltages employed in the final design. In reality, considering leakage power the energy-voltage curve is not simply monotonically increasing and there is still no optimal polynomal polynomial time algorithm. However, under the assumption that energy-voltage curve is quasiconvex, which is also a good approximation to actual situation, the optimal solution can be got in time O(nk2). Experimental results show that our algorithms are more efficient than previous works.

In this paper, we propose a novel feature named histogram of template (HOT) for human detection in still images. For every pixel of an image, various templates are defined, each of which contains the pixel itself and two of its neighboring pixels. If the intensity and gradient values of the three pixels satisfy a pre-defined function, the central pixel is regarded to meet the corresponding template for this function. Histograms of pixels meeting various templates are calculated for a set of functions, and combined to be the feature for detection. Compared to the other features, the proposed feature takes intensity as well as the gradient information into consideration. Besides, it reflects the relationship between 3 pixels, instead of focusing on only one. Experiments for human detection are performed on INRIA dataset, which shows the proposed HOT feature is more discriminative than histogram of orientated gradient (HOG) feature, under the same training method.

In this paper, a workload estimation scheme is proposed for surveillance video encoding by using difference detection and Hilbert transform-based workload estimation model. Difference detection distributes the input video data according to their content similarity features and retrieves the encoding workload for the coded frames. Workload estimation model predicts the encoding workload for the following time slot using Hilbert transform and error control. Experimental results indicate that the proposed workload estimation model can provide accurate estimation results without performance hit to maintain the video encoding performance under a given performance constraint during power reduction.

In this paper, a feature for human detection from still image is proposed. A multi scale block histogram of template feature (MB-HOT) is developed for human detection by extending the template level in the feature extraction. It integrates gray value information and gradient value information, and reflects relationship of three blocks. The feature is extracted from more macrostructures level and could represent more characteristic of human body. Experiment on INRIA dataset shows that this feature is more discriminative than other features, such as histogram of orientation gradient (HOG). Graphic process unit (GPU) based implementation is proposed to accelerate the calculation of two features, and make it suitable for real time application.

In this paper, a hardware-efficient fast algorithm with a lossless frame recompression scheme for large search range (SR) motion estimation (ME) utilized in ultra high definition video encoder is presented. To ensure high ME quality for hierarchical motion search, the advanced hierarchical ME scheme which processes the multi-resolution search with a coarse-to-fine strategy in parallel is proposed. This enables high data and hardware reuse for much lower bandwidth and memory cost, which at the same time maintains ME quality. Furthermore, a lossless frame recompression scheme based on this ME algorithm to further reduce DRAM bandwidth is presented. An efficient leveling memory organization as well as a leveling two-step data fetching strategy is proposed to meet constrains of random access for hierarchical motion search structure. Experimental results show that the total scheme increases PSNR by an average of 0.03dB with a much less bit rate increasing compared with previous works especially for high motion sequences, while achieving a considerable saving of memory and bandwidth cost for large SR of [-128, 127].

In this demo, a low power H.264/AVC video encoding system is demonstrated for surveillance video compression, which is based on our proposed algorithms as difference detection and Hilbert transform based workload estimation. Two surveillance video coding schemes (with and without our proposed methods, respectively) are implemented on multi-core embedded platform and compared side by side. The power consumption of each encoding scheme is measured during video encoding and displayed explicitly to show a more than 60% power reduction introduced by the proposed methods. The reconstructed video is also synchronized and displayed as the video is encoded to present a maximum of 50 times higher encoding speed.

Owing to the huge bandwidth requirement, the DRAM power composes a significant portion of the power consumed by video coding system. In this paper, a lossless frame recompression scheme for reducing DRAM bandwidth is presented. The basic structure of the scheme which includes the memory organization, the data fetching strategy as well as the cache organization is proposed. Furthermore, an adaptive DPCM (Differential Pulse Code Modulation) scanning order selection is used and an efficient coding method that is suitable for compressing the DPCM samples in reference frames is also discussed. Experimental results show a 50%~60% saving of bandwidth on 720p and 1080p sequences, which indicates that the proposed scheme can be useful in reducing the system power through saving DRAM bandwidth.

Based on the particular structure of parity check matrix (PCM) of LDPC codes in WiMAX and WiFi wireless communication standards, a new early stopping criterion (SC) is proposed to save the unnecessary decoding iterations. By using the proposed SC, decoding process will be stopped if all the information bits in a code word are corrected even if there are still some errors in the redundant (parity) part. Simulation shows that our proposed SC outperforms previous ones on decoding speed evaluated by average iteration number (AIN) with no bit error rate (BER) performance loss.

In high definition video decoders for the standard like H.264, bandwidth requirement is a critical design issue due to the overwhelming amount of memory data access. This paper proposes a new adaptive reference frame compression scheme to reduce external memory bandwidth consumption. An efficient variable length coding is proposed to compress each processing unit efficiently. Moreover, an adaptive compression mode decision unit is proposed to adaptively choose the best compression mode according to the image characteristic and bandwidth requirement. As a result, the proposed scheme achieves efficient bandwidth reduction with little image quality loss. The experimental results show that, at the same bandwidth reduction ratio the proposed algorithm achieves up-to 0.7 dB gain compared to the existing approaches.

Transmission of compressed video over error prone channels may result in packet losses or errors, which can significantly degrade the image quality. Such degradation even becomes worse in 1Seg video broadcasting, which is widely used in Japan and Brazil for mobile phone TV service recently, where errors are drastically increased and lost areas are contiguous. Therefore the errors in earlier concealed MBs (macro blocks) may propagate to the MBs later to be concealed inside the same frame (spatial domain). The error concealment (EC) is used to recover the lost data by the redundancy in videos. Aiming at spatial error propagation (SEP) reduction, this paper proposes a SEP reduction based EC (SEPEC). In SEPEC, besides the mismatch distortion in current MB, the potential propagated mismatch distortion in the following to be concealed MBs is also minimized. Also, 2 extensions of SEPEC, that SEPEC with refined search and SEPEC with multiple layer match are discussed. Compared with previous work, the experiments show SEPEC achieves much better performance of video recovery and excellent trade-off between quality and computation in 1Seg broadcasting in terms of computation cost.

This paper proposes a high-performance intra prediction architecture that can support H.264/AVC high profile. The proposed MB/block co-reordering can avoid data dependency and improve pipeline utilization. Therefore, the timing constraint of real-time 4k×2k encoding can be achieved with negligible quality loss. 16×16 prediction engine and 8×8 prediction engine work parallel for prediction and coefficients generating. A reordering interlaced reconstruction is also designed for fully pipelined architecture. It takes only 160 cycles to process one macroblock (MB). Hardware utilization of prediction and reconstruction modules is almost 100%. Furthermore, PE-reusable 8×8 intra predictor and hybrid SAD & SATD mode decision are proposed to save hardware cost. The design is implemented by 90nm CMOS technology with 113.2k gates and can encode 4k×2k video sequences at 60 fps with operation frequency of 310MHz.

Depth map coding is a new topic in multiview video coding (MVC) following the development of depth-image-based rendering (DIBR). Since depth map is monochromatic and has less texture than color map, fast algorithm is necessary and possible to reduce the computation burden of the encoder. This paper proposed difference detection based early mode termination strategy. The difference detection (DD) algorithms are categorized to reconstructed frame based (RDD) and original frame based (ODD). A simplified ODD (sODD) strategy is also proposed. Early mode termination based on these three DD algorithms are implemented and evaluated in the reference software of Joint Multiview Video Coding (JMVC) version 8.0 respectively. Simulation results indicate that RDD based one has no performance lost and reduce 25% runtime on average. ODD and sODD based ones can save 54.3% and 43.6% runtime respectively and have an acceptable R-D performance lost.

In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard. The design is based on a novel sum-delta message passing schedule to achieve high throughput and low area cost design. We further improve the design with pipeline structure and parallel computation. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.

In H.264/AVC based integer motion estimation engine, fixed architectures based on full pixel or direct sub-sampling pattern are widely used for HDTV application. However, these architectures suffer from either high complexity or quality loss problems. In this paper, an adaptive sub-sampling based reconfigurable architecture is given out. Firstly, by executing pixel difference analysis, the adaptive sub-sampling scheme which uses three hardware friendly patterns is applied on homogeneous macroblock (MB). Secondly, the related architecture introduces one more pipeline stage to build up configurable partial SAD values so that system performance is enhanced. Thirdly, a two-level pixel data organization scheme is proposed to solve data reuse and hardware utilization problems caused by adaptive algorithm. Moreover, one cross based SAD generation structure is introduced to achieve adaptive output results with less hardware cost. Experimental results show that, the proposed architecture can averagely save 61.71% clock cycles and accomplish twice or four times processing capability for homogeneous MBs. The maximum clock frequency is 208MHz under the TSMC 0.18um technology in worst case conditions(1.62V, 125 C).

Power optimization has become a significant issue when the CMOS technology entered the nanometer era. Multiple-Supply Voltage (MSV) is a popular and effective method for power reduction. Level shifters may cause area and Interconnect Length Overhead(ILO), and should be considered during floorplanning and post-floorplanning stages. In this paper, we propose a two phases framework VLSAF to solve voltage and level shifter assignment problem. At floorplanning phase, we use: a convex cost network flow algorithm to assign voltage; a minimum cost flow algorithm to assign level shifter. At post-floorplanning phase, a heuristic method is adopted to redistribute white spaces and calculate the positions and shapes of level shifters. Experimental results show VLSAF is effective.

Because of the outstanding contribution in removing pixel correlation, block-based transform and quantization has been widely accepted in the state-of-art image/video coding standards. However, artifacts are introduced, which result in reducing the subjective quality of the decoded image/video. In this paper, a composite model of the optical flow velocity is mathematically derived and proved to further reduce the blocking artifacts by compensating the DC surface of the decoded image according to the model. The functional relationship among the optical flow velocity of the DC surface of the decoded image, the value discontinuity across the block boundary in the decoded image and the quantity of DC surface adjustment is analyzed and mathematically modeled as a composite function with second-degree polynomial. Four feature points on the model with the corresponding criteria in artifacts reduction are compared to show a good consistency between the model and the actual filtering effects. Finding a point on the model with a better trade-off between the optical flow smoothness and the edge smoothness is promising in producing a more pleasing and natural looking image/video.

In this paper, we present a high-throughput deblocking filter architecture for H.264/AVC in QFHD applications. In order to enhance the parallelism of filtering without notably increasing the area, we propose to parallelize the processing of luminance and chrominance samples, instead of simultaneously filtering two edges of a same component. Although the edge filter and transpose cost of the proposed architecture is a little larger than that of the single-filter solution, control logic is saved by applying an identical processing schedule to both the luminance and chrominance samples. Meanwhile, total SRAM size by bit is kept unchanged when the architecture is parallelized. As a result, throughput of this work is advanced by 50% (or processing time reduced by 33%), to be 136 cycles/MB, while area cost (17.9 k gates logic and 8 k bits SRAM) is kept comparable to the state-of-the-art works.

In this paper, we present a cache scheme targeting hardware implementation to reduce the bandwidth of motion compensation, and a block-pipelining strategy to hide long latency of the external memory in high definition H.264/AVC video decoder. Hardware architecture is also implemented for the proposed algorithms. Experimental results show that the cache succeeds in reducing external memory bandwidth of motion compensation by 66%∼78% and the block-pipelining strategy can solve the latency problem better than previous solutions. Our proposed hardware architecture can averagely process one macroblock within 297 cycles, capable of real-time processing 1920×1088@30fps H.264 sequence at lower than 80MHz.

With recent advance of VLSI design, interconnect delay plays dominant role in the chip performance. 3D integration, which stacks multiple device layers, greatly reduces interconnect delay. Buffer insertion, as another approach to reduce wire delay, is still necessary to further optimize interconnects. In this paper, a buffer planning algorithm at floorplanning stage for 3D ICs is proposed. Firstly, we reduce buffer insertion to a dynamic programming path problem. Then we show its potential to handle the 3D buffer insertion problem. At the same time, vertical interlayer vias are also planned. At last, buffer planning is integrated with floorplanning to optimize the packing so that not only area and wire length reach a satisfying value, timing performance is also optimized.

The Cell Broadband Engine Architecture (CBEA) is an excellent architecture for high performance distributed computing and multimedia processing. While the Cell/BE processor is capable of high definition H.264 encoding, there are still no such implementations available. In this paper, we present a parallel implementation of a HD H.264 encoder on this heterogeneous nine cores processor. First we implement a real time SD encoder on a single SPU by optimizing Motion Estimation algorithm, DMA transfers etc. Then we propose a pipelined parallel encoding algorithm for multicore processors, and use this algorithm to get a real time HD H.264 encoder (1920×1080@31fps) by using eight SPEs (58fps on 16 SPEs).

In this paper, a new human detection approach from still image is proposed. Two vector features are extracted from the image. Histogram of oriented gradient feature represents the gradient information of human. Histogram of modified local binary pattern is extracted from images convolved with Gabor filter, as a feature vector to represent texture information. It can be seen as a supplement of gradient information. Different support vector machine classifiers are trained by each type of vectors. Finally, two classifiers are combined together for the final result by using the proposed integration method. Because two features contain different information, they have low error dependency and can get high detection rate. Experiment is performed in a large dataset and it shows that this method outperforms state-of-the-art approaches and other combinations of features.

Transmission of compressed video over error prone channels may result in packet losses or errors, which can significantly degrade the image quality. Such degradation even becomes worse in 1Seg video broadcasting application, which is widely used in Japan and Brazil for mobile phone TV service, where errors are drastically increased and huge conjunctive areas inside a picture may be corrupted. In this case the error concealment order -to decide which MB should be concealed earlier -may highly influence image quality. Aimed this problem, this paper proposes an adaptive concealment order based on well-known boundary matching algorithm (BMA). The concealment order is carefully chosen according to a lost MB's priority, which is formulated considering a concealed MB's side match distortion: an MB with smaller distortion should be concealed earlier compared with an MB with larger distortion. As for formulation of side match distortion, not only the current corrupted MB's, but also the neighboring MB's, which is caused by error propagation, are included. Compared with reference work [10], the experiments show our proposal achieves better performance of video recovery under different error rate channel in 1Seg application.

In the latest video coding frameworks, efficiency of motion vector (MV) coding is becoming increasingly important because of the growing bit rate portion of motion information. In this paper, we present a prioritized reference decision scheme for MV coding based on the H.264/AVC framework. This scheme makes use of a boolean indicator coded into the modified code words of mb_type and sub_mb_type, so as to designate whether the conventional median prediction or an alternative reference decision method is to be used. If the latter is indicated, a validation function is applied to a prioritized list of neighboring MVs, so that the minimum-cost MV difference (MVD) is likely to be generated using multiple reference MVs, with no extra overhead. Experimental result shows the proposed scheme achieves considerable bit rate reduction on MVDs, when compared with the conventional median prediction method. It also achieves a better and much stabler performance than the state-of-the-art MBP-based MV coding. Meanwhile, the harmful feedback issue of MBP is prevented in the proposed scheme.

Region-of-interest (ROI) can be applied in H.264 video encoder to enhance subjective quality and reduce computation complexity. For the aiming application of low cost hardware real-time encoder in videophone with faces as ROI, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification process and can be combined with a H.264 encoder by MB level pipeline architecture. 97.91% MBs in faces can be detected. VLSI architecture of proposed face detection algorithm is designed and an area of 4.3 k gates is achieved. Power consumption is only 1.45 mW at 100 MHz. A ROI based H.264 encoder with dynamic parameters is proposed to enhance subjective quality and reduce the rate-distortion-optimization (RDO) complexity. The PSNR in ROI increases for 4.8 dB under similar bit rate. Encoding time is reduced to 54.4% in videophone-like sequences.

The block-based prediction, transform and quantization reduce the redundancy in video data efficiently. However, the blocking artifacts are introduced because of quantization error and prediction scheme. Even if the de-blocking filter is applied like that designed in H.264 and AVS, the blocking artifacts are still visible especially in videos with smooth area coded at low bit-rate. In this paper, an optical flow based technique is proposed to further reduce the blocking artifacts by compensating the DC surfaces of the decoded images using joint optimization of optical flow and edge difference. The proposed algorithm automatically classifies the macroblocks in the decoded images according to their texture feature and endures the smooth area with smooth brightness variation by minimizing the joint function of optical flow magnitude and edge smoothness. It produces a more pleasing image without over-filtering, which can be further applied as an in loop filter for video coding.

Since H.264 is a high performance coding standard in with high computational requirements, it is hard to implement on portable devices. According to the human visual system (HVS) research, human eyes can only focus on one area in a frame, which is called region-of-interest (ROI). This phenomenon gives a chance to code all macroblocks unequally. In this work, the ROI is detected using texture contrast and motion features. This detector uses a simple scheme to meet the low power requirement of portable application. After getting ROI, coding parameters, in terms of search ranges, and valid modes, are allocated in ROI and non-ROI respectively. This strategy reduces the coding complexity and keeps the visual quality. The ROI detector and the encoder are designed to be decoding-friendly and hardware-friendly.

The H.264/AVC coding standard processes variable block size motion-compensated prediction with multiple reference frames to achieve a pronounced improvement in compression efficiency. Accordingly, the computation of motion estimation increases in proportion to the product of the number of reference frame and the number of intermode. The mathematical analysis in this paper illustrates that the motion-compensated prediction errors are mainly determined by the detailed textures in the source image. The image block being rich in textures contains numerous high-frequency signals, which make variable block size and multiple reference frame techniques essential. On the basis of rate-distortion theory, in this paper, the spatial homogeneity of an image block is made as a relative concept with respect to the current quantization step. For the homogenous block, its futile reference frames and intermodes can be eliminated efficiently. It is further revealed that the sum of absolute differences value of an image block is mainly determined by the sum of its edge gradient amplitude and the current quantization step. Consequently, the image content-based early termination algorithm is proposed, and it outperforms the original method adopted by JVT reference software. Moreover, the dynamic search range algorithm based on the edge gradient amplitude of source image block is analyzed. One eminent advantage of the proposed edge-based algorithms is their efficiency to the macroblock-pipelining architecture, and another desirable feature is their orthogonality to fast block-matching algorithms. Experimental results show that when these algorithms are integrated with hybrid unsymmetrical-cross multi-hexagongrid search, an averaged 31.4-60.0% motion estimation time can be saved, whereas the averaging BDPSNR loss is 0.0497 dB for all tested sequences.

The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced mismatch. As the development of VLSI technology, the random mismatch is becoming more and more serious. And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch. Therefore, in this paper, we first propose a new model which can estimate the combination effect of both random mismatch and thermal-induced mismatch by mismatch analysis and SPICE simulation. And in order to meet the different sensitivities of different symmetry pairs, an automatic classification tool and a configurable optimization process are also introduced. All of these are embedded in the floorplanning process. The final experimental results prove the effectiveness of our method.

To reduce the miss rate of the instruction cache, a hardware-assisted loop optimization method is proposed in this paper. This method utilizes the hardware/software co-design strategy on the behavior level. Especially, this method is equipped with the specific instruction set to limit the cache misses, which can be viewed as a set of hardware for special purposes. Then based on the specific instruction set, a scheduling process is integrated which reduces the cache miss rate through the code transformation. Finally, a set of benchmarks from MediaBench1.0 are tested on the SimpleScalar platform to assist the proposed method. The final experiments indicate that 26% enhancement can be obtained for the cache miss reduction, where the specific instruction generation and the scheduling processes contribute about 23% and 3% respectively.

A partially-parallel decoder architecture for irregular LDPC code targeting high throughput and low cost applications is proposed. The design is based on a novel sum-delta message passing algorithm that facilitates the decoding throughput by removing redundant computations and decreases the hardware cost by optimizing the storage. Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.

This paper presents an efficient hybrid memory access optimization system called HyMacs, which integrates the hardware and software optimization strategies in the embedded system design. First, HyMacs features a pre-configuration stage which is equipped with a memory configuration algorithm to satisfy area constraints. Then a custom instruction generation process is integrated in the system via a seed-growth algorithm under the intelligent guide functions. The custom instruction benefits to the reduction of the whole memory access latency and thus relieves the burden of system through hardware mode. Finally, a data-dependency-driven scheduling algorithm is also integrated to compress the whole latency through access mode conversion. We have tested the system on a set of commonly used benchmarks, and compared the results with the previous memory access system MACCESS-opt proposed in DAC'05. The experimental results indicate 20% enhancement obtained for the total memory access latency reduction compared with MACCESS-opt, where the custom instruction generation and scheduling contribute about 15% and 5% respectively.

Fixed-outline floorplanning, which enables hierarchical design, is considered more and more important nowadays. In this paper, a novel SA-based Fixed-outline Floorplanner with the Optimal Area utilization named SAFFOA is introduced to improve the total wirelength. The basic idea is to build and solve a group of four quadratic equations in four variables iteratively, which can handle the fixed-outline constraint of any aspect ratio. A new topological representation called Ordered Quadtree is then custom-made for this basic idea to facilitate its integration into SA iterations. After the fixed-outline constraint with 100% area utilization is achieved, we will solve the tradeoff between the chip area and wirelength and thus concentrate on the latter in SA process. Experimental results show that the chip wirelength is decreased by about 16.8% and 8.6% on average, compared with two previous fixed-outline floorplanners on soft modules, which are both proved to be better than Parquet. Besides, our method is still competitive on the wirelength, even if compared with some leading-edge outline-free floorplanners. At last, Local Refinement is also adopted to guide the SA process and reshape soft modules to meet the constraint on their aspect ratios (ARs). With its help, SAFFOA can still generate feasible floorplans with no deadspace under a strict AR constraint such as [0.5,2].

Variable block size motion estimation algorithm is the effcient approach to reduce the temporal redundancies and it has been adopted by the latest video coding standard H.264/AVC. The computational complexity augment coming from the variable block size technique makes the hardwired accelerator essential, especially for real-time applications. In this paper, the authors apply the architecture level and the circuits level approaches to improve the performance of Propagate Partial SAD and SAD Tree hardwired engines, which outperform other counterparts when considering the impact of supporting the variable block size technique. Experiments demonstrate that by using the proposed approaches, compared with the original architectures, 14.7% and 18.0% hardware cost can be saved for Propagate Partial SAD architecture and SAD Tree architecture, respectively. With TSMC 0.18 mm 1P6M CMOS technology, the proposed Propagate Partial SAD architecture attains 231.6 MHz operating frequency at a cost of 84.1 k gates. Correspondingly, the execution speed of the optimized SAD Tree architecture is improved to 204.8 MHz with 88.5 k gate hardware overhead.

The search range (SR) parameter plays an important role in motion estimation (ME) for video coding. Adaptively adjusting SR according to the information given by previously encoded syntax element, also known as adaptive search range (ASR) algorithm, can efficiently reduce the computational complexity of ME. Compared with heuristic search pattern (HSP) algorithms like diamond/hexagon search, ASR algorithms are more fundamental, flexible and hardware-oriented. This paper although starts with a comparison between HSP and ASP algorithms which is followed by a proposed ASR algorithm with experimental results, however more likely intends to contribute several novel perspectives to this research area.

The key to high performance in video coding lies on efficiently reducing the temporal redundancies. For this purpose, H.264/AVC coding standard has adopted variable block size motion estimation on multiple reference frames to improve the coding gain. However, the computational complexity of motion estimation is also increased in proportion to the product of the reference frame number and the inter mode number. The mathematical analysis reveals that the prediction errors mainly depend on the image edge gradient amplitude and quantization parameter. Consequently, this paper proposed the image content based early termination algorithm, which outperforms the method adopted by JVT reference software, especially at high and moderate bit rates. In light of rate-distortion theory, this paper also relates the homogeneity of image to the quantization parameter. For the homogenous block, its search computation for the futile reference frames and inter modes can be efficiently discarded. Then the computation saving performance increases with quantization parameter. These content based fast algorithms were integrated with Unsymmetrical-cross Multihexagon-grid Search (UMHexagonS) algorithm. Compared to the original UMHexagonS fast matching algorithm, 26.14-54.97% search time can be saved with an average of 0.0369dB coding quality degradation.

In this paper, a hardware-oriented fast fractional motion estimation (FME) algorithm for H.264/AVC is proposed. For both 1/2-pixel and 1/4-pixel FME, only 4 points are searched, and thus the required processing unit (PU) number is reduced from 9 to 4. Experiments show that the proposed algorithm can provide very similar image quality as full search, and the average PSRN drop is 0.17dB or bitrate increase is 4.08%. Compared with the full search FME hardware architecture [5], the proposed algorithm can effectively reduce about 32.3% hardware cost and thus is very suitable for low-cost and low-power applications.

In H.264/AVC standard, motion estimation (ME) can be executed on multiple reference frame (MRF) to improve the coding performance. For real-time hardwired encoder, the huge throughput of fractional motion estimation (FME) and integer motion estimation (IME) makes pipeline stage a must. So, IME is arranged in a single stage, which deteriorates the efficiency of many fast ME algorithms. This paper provides a VLSI friendly complexity reduction solution for ME procedure. Firstly, the proposed algorithm examines the pixel difference of current macroblock (MB) and adjust the available reference frame number. Secondly, it executes matching analysis to detect MB with static feature and early terminate the IME process. Thirdly, based on motion feature analysis result, the search range for non static MB is also adjusted and redundant search positions are eliminated. Compared with full search algorithm, the proposed fast ME algorithm can reduce 47.91% to 91.88% ME time with negligible video quality degradation. Furthermore, the algorithm can also be combined with other fast block matching process and friendly to hardwired encoder.

In the state-of-the-art video coding standard, H.264/AVC, the encoder is allowed to search for its prediction signals among a large number of reference pictures that have been decoded and stored in the decoder to enhance its coding efficiency. Therefore, the computation complexity of the motion estimation (ME) increases linearly with the number of reference picture. Many fast multiple reference frame ME algorithms have been proposed, whose performance, however, will be considerably degraded in the hardwired encoder design due to the macroblock (MB) pipelining architecture. Considering the limitations of the traditional four-stage MB pipelining architecture, two fast multiple reference frame ME algorithms are proposed here. First, on the basis of mathematical analysis, which reveals that the efficiency of multiple reference frames will be degraded by the relative motion between the camera and the objects, for the slow-moving MB, the authors adopt the multiple reference frames but reduce their search range. On the other hand, for the fast-moving MB, the first previous reference frame is used with the full search range during the ME processing. The mutually exclusive feature between the large search range and the multiple reference frames makes the computation saving performance of the proposed algorithm insensitive to the nature of video sequence. Second, following the Hadamard transform coefficient-based all_zeros block early detection algorithm, two early termination criteria are proposed. These methods ensure the pronounced computation saving efficiency when the encoded video has strong spatial homogeneity or temporal stationarity. Experimental results show that 72.7%-93.7% computation can be saved by the proposed fast algorithms with an average of 0.0899 dB coding quality degradation. Moreover, these fast algorithms can be combined with fast block matching algorithms to further improve their speedup performance.

The intra-frame coding in H.264/AVC has made significant contribution to the enhancement of coding efficiency. However it brings about a heavy computation burden in the rate distortion based (RD) mode decision (MD) process. Although the real-time encoding of 1280-720p signals is realized in recent works with existing algorithms, for higher resolution e.g. 1920-1088p some hardware-oriented fast algorithms are necessary. Yet so far few of the many proposed fast MD algorithms have seen successful hardware implementation. This paper presents a novel VLSI design (15.8k [email protected], with TSMC CMOS 0.18μm technology) of an edge based fast intra MD algorithm which can constantly reduce about 66% of the RD related computation with a negligible quality loss. It is expected to be utilized as a favorable accelerator hardware module in a real-time HDTV (1920-1088p) H.264 encoder or MPEG2-H.264 transcoder.

One hardware efficient and high speed architecture for variableblock size motion estimation in H.264 is presented in this paper. Through compressing the propagated data and optimizing theprocessing element and adder tree circuits in pipeline, this architecture gets more hardware efficient datapath logic. Compared with the original Propagate Partial SAD structure, 12.1% hardware cost can be saved. With TSMC 0.18μm CMOS 1P6M standard celllibrary, the maximum clock speed of this design is 227MHz in worstwork conditions (1.62V, 125°C). With the 48x32 search range, the maximum throughput of our design is 147786 MB/S, which can be used in the real-time encoding of VGA resolution frame with 4 reference frames at 30Hz.

In H.264/AVC standard, motion estimation can be processed on multiple reference frames (MRF) to improve the video coding performance. For the VLSI real-time encoder, the heavy computation of fractional motion estimation (FME) makes the integer motion estimation (IME) and FME must be scheduled in two macro block (MB) pipeline stages, which makes many fast MRF algorithms inefficient for the computation reduction. In this paper, two algorithms are provided to reduce the computation of FME and IME. First, through analyzing the block's Hadamard transform coefficients, all-zero case after quantization can be accurately detected. The FME processing in the remaining frames for the block, detected as all-zero one, can be eliminated. Second, because the fast motion object blurs its edges in image, the effect of MRF to aliasing is weakened. The first reference frame is enough for fast motion MBs and MRF is just processed on those slow motion MBs with a small search range. The computation of IME is also highly reduced with this algorithm. Experimental results show that 61.4%-76.7% computation can be saved with the similar coding quality as the reference software. Moreover, the provided fast algorithms can be combined with fast block matching algorithms to further improve the performance.

Variable block size motion estimation (VBSME) is the most computation consuming part in the newest H.264 /AVC video coding standard. To reduce computation, an ultra low-complexity fast VBSME algorithm is proposed in this paper. Different to previous fast algorithms which separately pressed the 7 block modes, in the presented algorithm, all the block modes are simultaneously calculated for most of the search points, and thus the SADs can be reused by all blocks. Moreover, a low-pass filter based pixel decimation is also introduced to decrease the matching cost. Experiments show that the proposed fast VBSME algorithm can reduce the computation to about 0.2% of fast full search (FFS) with robust image quality.

In MPEG-2 to H.264 transcoding, MPEG-2 motion vector (MV) is often reused as search center to simplify H.264 motion estimation (ME) module. In this paper, we show that motion vector predictor (MVP) from neighboring sub-blocks is more accurate than MPEG-2 MV as search center when MPEG-2 MV field is non-smooth. A criterion based on relative motion is proposed to evaluate smoothness of MPEG-2 MV field. And a hardware oriented MV prediction scheme is also proposed. Experiment results show that the proposed MV prediction scheme with a relative small search range can approach the performance of full search algorithm. Comparing with the method only utilizing MPEG-2 M V, the proposed approach can achieve significant improvement on accuracy of motion prediction, especially in sequences with fast motion and complicate background.

This paper presents an enhanced strict multilevel successive elimination algorithm (EMSEA) for fast block-matching motion estimation, which is based on the previous strict multilevel successive elimination algorithm (SMSEA) (Song et al., 2006). Different to the SMSEA algorithm with fixed parameters, in EMSEA algorithm, the whole search area is divided into two regions and each region has its own parameters. Therefore, the computation complexity of SMSEA algorithm can be further decreased. Experiments show that the proposed EMSEA algorithm can reduce 16.2% of the SMSEA computation and maintain almost the same image quality, which is better than the TSS and DS algorithms.

Motion estimation (ME) is a computation-intensive operation in video coding system. In MPEG-2 to H.264 transcoding, motion vector (MV) from MPEG-2 reused as search center in H.264 encoder is a simple but effective technique to simplify ME procedure. However directly introducing MPEG-2 MV will bring irregular overlapping between search windows of successive macroblocks (MB) which invalidates the data reuse scheme in hardware design of ME module. In this paper, the authors propose a search window reuse scheme for transcoding in HDTV application. By utilizing the similarity between neighboring MVs, overlapping of search windows between successive MBs can be regularized. Experiment results show that our method achieve average 93.1% search window reuse rate in HDTV sequence with almost no video quality degradation. And the bandwidth can be reduced to 92.5 Mbytes/s based on theoretical calculation which is only 40.6% of that without this scheme.

This paper proposes the power-efficient LDPC decoder architecture which features (1) a FIFO buffering based rapid convergence schedule which enables the decoder to accelerate the decoding throughput without increasing the required number of memory bits, (2) an intermediate message compression technique based on a clock gated shift register which reduces the read and write power dissipation for the intermediate messages. Simulation results show that the proposed decoder achieves 1.66 times faster decoding throughput, and improves the power efficiency (which is defined by the power dissipation per Mbps) up to 52% compared to the decoder based on the conventional overlapped schedule.

We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304 bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 530Mb/s at an operating frequency of 147MHz. The chip has been fabricated in a 0.18mum, 6 metal-layer CMOS technology. The chip size is 36mm2

In this paper, a fast motion estimation algorithm, which is friendly to VLSI hardware implementation is proposed. This algorithm has such features: First, through "Haar" low-pass filter based subsampling, the computation complexity at each search position is reduced to about 25% of the original algorithm; Second, one modified motion vector prediction is provided to eliminate the data dependence among sub-partitions in the same macro block (MB). Based on this approach, parallel processing for variable block size motion estimation (VBSME) with integer pixel accuracy can be realized; Third, one "adaptive sub-search window" scheme is proposed to further reduce computation cost and it also can facilitate reference frame data reusing to reduce memory transfer from the external RAM to the on-chip SRAM. The proposed VBSME algorithm is very suitable for parallel VLSI implementation

Motion estimation (ME) requires huge computation complexity. Many motion estimation algorithms have been proposed to reduce its complexity. But they are still insufficient for embedded video coding systems. So we proposed an ultra-low complexity ME algorithm that is suitable for the software implementation. The simulation results show that proposed algorithm has about 1,000 times the speedup than full search (FS) maintaining high image quality. And we also propose an application specific instruction-set processor (ASIP) for ME. It is based on a reduced instruction set computer (RISC) with sum of absolute difference (SAD) operation circuit. Our ME ASIP is implemented on FPGA. It is required about 3,313 logic elements (LEs) and its hardware scale is about quarter of the previous ME ASIP. This ME ASIP makes a significant contribution to the development of compact video coding systems

This paper proposes a parallel LSI architecture for LDPC decoder which improves a message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) the column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently; and (ii) the proposed parallel pipelined bit functional unit enables the decoder to perform every column operation using the messages which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay. Hardware implementation and simulation results show that the proposed decoder improves the decoding throughput and bit error performance with a small hardware overhead

Fractional motion estimation (FME) on sub-pixels will occupy almost over 45% of the computation complexity of H.264 encoding process. Therefore a high performance VLSI architecture of FME is described in this paper to achieve the capacity of encoding the high-resolution real-time video stream for HDTV. Our design is improved from an existing work by involving a pipeline strategy in sub-pixel interpolation unit which can avoid the long delay paths in 6-tap ID FIR so as to increase the clock frequency up to 200MHz. Moreover, a 16-pixel search engine is adopted to remove the redundant interpolation area and parallelize the various block size search which can save more than half of the clock cycles in processing a macro block. Our design is implemented with only 189K gates at operating frequency of 200MHz in worst case (285MHz in typical case). It can provide the processing capacity of more than 250K MB/sec which is enough for 1080HD (1920times1088) video streams at frame rate of 30fps. It is a useful intellectual property (IP) design for multimedia system

Edge detection is a vital pre-processing step of many image analysis systems. In this paper, we intend to present a novel algorithm to automatically extract color image edge by integrating multi-dimensional gradient analysis and statistical analysis on local regions. Compared with previous gradient-based edge detection algorithms, our algorithm does not need to select an appropriate threshold against the gradient magnitude. With an elaborate edge detector, we exploit image pixel gradient direction, magnitude, spatial information and region property to obtain color image edge. To avoid the problem of detecting false edges, we conduct statistical analysis on certain local regions, which have high edge density, to further optimize our edge detection result. Experimental results demonstrate the performance of our algorithm on different color images.

This paper proposes an inter-symbol interference (ISI) suppression scheme using the periodic signal waveform for fixed-rate coded OFDM systems. In this scheme, the periodic signal waveform composed of the even-numbered sub-carrier group is used for extending the guard interval, and the odd-numbered sub-carrier group is also enable to be available by means of frequency conversion in order to realize the sub-carrier group selection. This paper mainly focuses on the combining effect of the sub-carrier group selection and the channel coding scheme in the inter-symbol interference (ISI) condition. Computer simulation results show that the proposed scheme has the great potential to create the combined frequency diversity effect without the error floor even in the severe ISI condition.

In this paper, we present an efficient architecture for deblocking filter in H.264/AVC. A novel 2-dimensional parallel memory scheme is employed in order to achieve highly efficient parallel access in both horizontal and vertical directions. By using this parallel memory scheme, we also eliminate the need for a transpose circuit. Our design is implemented under 0.35/spl mu/m technology. Synthesis results show that the equivalent gate count is only 9.35K (not including SRAMs) when the maximum frequency is 100MHz.

This paper proposes a reconfigurable adaptive FEC system with interleaving. For adaptive FEC schemes, we can implement an optimal RS decoder composed of minimum hardware units for any given error correction capability t. If the hardware units of the RS decoder can be reduced for any given t, we can embed as large deinterleaver as possible into the RS decoder for each t. Reconfiguring the RS decoder embedded with the expanded deinterleaver dynamically for each t allows us to decode larger interleaved codes which are more robust FEC codes to burst errors. Our reconfigurable adaptive FEC system with interleaving achieves better packet error rate and higher throughput than fixed hardware systems.

Many parallel Fast Fourier Transform (FFT) algorithms adopt multiple stages architecture to increase performance. However, data permutation between stages consumes volume memory and processing time. An FFT array processing mapping algorithm is proposed in this paper to overcome this demerit. In this algorithm, arbitrary 2k butterfly units (BUs) could be scheduled to work in parallel on n=22 data (k=0, 1,..., s-1). Because no inter stage data transfer is required, memory consumption is reduced to 1/3 of the original algorithm. Moreover, with the increasing of BUs, not only does throughput increase linearly, system latency also decreases linearly. This array processing orientated architecture provides flexible tradeoff between hardware cost and system performance. An 18-bit word-length 1024-point FFT architecture with 4 BUs is given to demonstrate this mapping algorithm. The design is implemented with TSMC 0.18μm CMOS technology. The core area is 2.99x1.12mm 2 and clock frequency is 326MHz in typical condition (1.8V, 25°C). This processor could complete 1024 FFT calculation in 7.839μs.

This paper proposes a partially-parallel LDPC decoder based on a high-efficiency message-passing algorithm. Our proposed partially-parallel LDPC decoder performs the column operations for bit nodes in conjunction with the row operations for check nodes. Bit functional unit with pipeline architecture in our LDPC decoder allows us to perform column operations for every bit node connected to each of check nodes which are updated by the row operations in parallel. Our proposed LDPC decoder improves the tuning when the column operations are performed, accordingly it improves the message-passing efficiency within the limited number of iterations for decoding. We implemented the proposed partially-parallel LDPC decoder on an FPGA, and simulated its decoding performance. Practical simulation shows that our proposed LDPC decoder reduces the number of iterations for decoding, and it improves the bit error performance with a small hardware overhead.

Text detection in color images has become an active research area since recent decades. In this paper, we present a novel approach to accurately detect text in color images possibly with a complex background. First, we use an elaborate edge detection algorithm to extract all possible text edge pixels. Second connected component analysis is employed to construct text candidate region and classify part non-text regions. Third each text candidate region is verified with texture features derived from wavelet domain. Finally, the expectation maximization algorithm is introduced to binarize text regions to prepare data for recognition. In contrast to previous approach, our algorithm combines both the efficiency of connected component based method and robustness of texture based analysis. Experimental results show that our algorithm is robust in text detection with respect to different character size, orientation, color and language and can provide reliable text binarization result.

Object detection is a critical step of many image recognition systems. In this paper, we discussed the circular shape object detection problem in still color images. The proposed method has an important feature of integrating color image edge extraction result with a novel circle parameter determination algorithm efficiently. First, an accurate isotropic edge detector is introduced to extract color image edge and calculate precise gradient direction of each potential edge pixel, which assures the high accuracy of subsequent circle detection. Then the detected potential edge results are verified by integrating them with spatial information and the result of region based analysis. Second we utilize just only one 2-dimensional accumulator array and one 1-dimensional accumulator array, which greatly reduce storage requirement and time complexity, to detect circles of any radius. Furthermore, the validity of detected potential circle centers is checked to avoid detecting false circles. Experimental results show that our method is robust and effective in locating objects with complete or incomplete or concentric circle boundary in real color images without any prior knowledge.

This paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size designed by using the proposed layout method is only 1.2-1.4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective for achieving a minimal chip layout design.

This paper describes an automatic/interactive layout design system for designing master-slice LSI chips, which places function blocks and gives wiring patterns on the chip. Since 100% routing is essential for master-slice layout design, it is urgently required to establish a strong CAD system, which significantly reduces the design time. The LAMBDA system has been developed to achieve complete net connectivity in as short a design time as possible, where efficient automatic procedures are implemented as well as highly interactive functions. The system adopts two-level hierarchy algorithms for placement and routing problems. Highly interactive functions are realized by exploiting human intelligence and the computer's high speed processing.