Yibin Yang 0001

dblp:75/5483-1 · DBLP profile ↗
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17ranked-venue papers
7as first author
16since 2021 · last 2026
0000-0001-6062-3531ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 15 · 7 first-author · 15 since 2021Systems, architecture and hardware · 3 · 2 since 2021Theory of computation · 1 · 1 first-author · 1 since 2021
YearPublicationVenuePosition
2026 Suffix-Invariant Programmable PRFs and Applications to Stacked Garbling
Vipul Goyal, David Heath 0001, Abhishek Jain 0002, Yibin Yang 0001
CRYPTO (8)4
2026 SumcheckPIM: An Efficient HBM-Based PIM Architecture for Linear Complexity Zero Knowledge Proofs
abstract
Zero-knowledge proofs (ZKPs) are emerging as a core technology for privacy-preserving computation. Despite steady progress in protocol and algorithm design, generating these proofs remains computationally intensive, driving growing interest in hardware acceleration for kernels such as number-theoretic transform (NTT) and multi-scalar multiplication (MSM). Among them, the sumcheck protocol offers a compelling alternative with O(n) prover complexity compared to O(nlog n) for NTT-based approaches, yet our analysis reveals its execution is fundamentally memory-bound, with severely underutilized compute resources. This characteristic demands a memory-centric acceleration strategy, in contrast to compute-centric approaches of prior work.
Sunchae Kim, Taewoon Kang, Sangwon Shin, Taeweon Suh, Yibin Yang 0001, Gunjae Koo
ICS5
2026 Scalable Off-Chain Auctions
Mohsen Minaei, Ranjit Kumaresan, Andrew Beams, Pedro Moreno-Sanchez, Yibin Yang 0001, Srinivasan Raghuraman, Panagiotis Chatzigiannis, Mahdi Zamani, Duc Viet Le 0001
NDSS5
2025 SoundBoost: Effective RCA and Attack Detection for UAV via Acoustic Side-Channel
abstract
Unmanned Aerial Vehicles (UAVs), or drones, are emblematic examples of cyber-physical systems where computational components and physical processes integrate to enable autonomous navigation. UAVs rely heavily on sensors such as Inertial Measurement Units (IMU) and Global Positioning System (GPS) for accurate environmental awareness and control. However, the trust placed in these sensors makes UAVs vulnerable to adversarial attacks that compromise the UAV’s operational integrity. While prior work focuses on detecting attacks against specific sensors, there remains a critical gap in performing Root Cause Analysis (RCA) to determine which component failed and why – especially under ambiguous or conflicting sensor reports. To address this gap, we propose SoundBoost, a novel RCA framework that leverages the UAV’s acoustic side-channel (i.e., sound) to diagnose navigation failures and attribute them to specific sensor compromises. While SoundBoost detects attacks by validating GPS and IMU sensor data, it focuses on post-incident diagnosis. SoundBoost conducts post-incident RCA by extracting robust acoustic signatures and using machine learning to cross-validate reported kinematics against physical behavior. We deploy SoundBoost on a UAV and evaluate it under real-world GPS spoofing attacks and synthesized IMU biasing attacks. SoundBoost achieves 100% true positive rate for IMU attacks and over 80% for GPS spoofing, outperforming the state-of-the-art by 21% – demonstrating its effectiveness as a practical forensic tool for sensor attack RCA.
Haoran Wang 0013, Sangdon Park 0001, Yibin Yang 0001, Seulbae Kim, Willian Tessaro Lunardi, Martin Andreoni, Taesoo Kim, Wenke Lee
DSN4
2025 Gold OPRF: Post-Quantum Oblivious Power-Residue PRF
abstract
We propose plausible post-quantum (PQ) oblivious pseudorandom functions (OPRFs) based on the Power-Residue PRF (Damgård CRYPTO'88), a generalization of the Legendre PRF. For security parameter$\lambda$, we consider the PRF Gold$k(x)$that maps an integer$x$modulo a public prime$p=2^{\lambda}\cdot g+1$to the element$(k+x)^{g}\text{mod}\ p$, where$g$is public and$\log g\approx 2\lambda$. At the core of our constructions are efficient novel methods for evaluating Gold within two-party computation (2PC-Gold), achieving different security requirements. Here, the server$\mathcal{P}_{s}$holds the PRF key$k$whereas the client$\mathcal{P}_{c}$holds the PRF input$x$, and they jointly evaluate Gold in$2\mathbf{PC}$. 2 PC-Gold uses standard Vector Oblivious Linear Evaluation (VOLE) correlations and is information-theoretic and constant-round in the (V)OLE-hybrid model. We show: •For a semi-honest$\mathcal{P}_{s}$and a malicious$\mathcal{P}_{c}$: a 2PC-Gold that just uses a single (V)OLE correlation, and has a communication complexity of 3 field elements (2 field elements if we only require a uniformly sampled key) and a computational complexity of$\mathcal{O}(\lambda)$field operations. We refer to this as half-malicious security. •For malicious$\mathcal{P}_{s}$and$\mathcal{P}_{c}$: a 2PC-Gold that just uses$\frac{\lambda}{4}+\mathcal{O}(1)$VOLE correlations, and has a communication complexity of$\frac{\lambda}{4}+\mathcal{O}(1)$field elements and a computational complexity of$\mathcal{O}(\lambda)$field operations. These constructions support additional features and extensions, e.g., batched evaluations with better amortized costs where$\mathcal{P}_{c}$repeatedly evaluates the PRF under the same key. Furthermore, we extend 2PC-Gold to Verifiable OPRFs and use the methodology from Beullens et al. (Eurocrypt'25) to get strong OPRF security in the universally composable setting. All the protocols are efficient in practice. We implemented 2PC-Gold-with (PQ) VOLEs-and benchmarked them. For example, our half-malicious (resp. malicious) n-batched PQ OPRFs incur about 100B (resp. 1.9KB) of amortized communication for$\lambda=128$.
Yibin Yang 0001, Fabrice Benhamouda, Shai Halevi, Hugo Krawczyk, Tal Rabin
SP1
2025 sfJustvengers: Batched VOLE ZK Disjunctions in 풪(R+B+C) Communication
Yibin Yang 0001
TCC (4)1
2024 Programmable Payment Channels
Ranjit Kumaresan, Duc Viet Le 0001, Mohsen Minaei, Srinivasan Raghuraman, Yibin Yang 0001, Mahdi Zamani
ACNS (3)5
2024 sfLogRobin++: Optimizing Proofs of Disjunctive Statements in VOLE-Based ZK
Carmit Hazay, David Heath 0001, Vladimir Kolesnikov, Muthuramakrishnan Venkitasubramaniam, Yibin Yang 0001
ASIACRYPT (5)5
2024 Tight ZK CPU: Batched ZK Branching with Cost Proportional to Evaluated Instruction
abstract
We explore Zero-Knowledge Proofs (ZKPs) of statements expressed as programs written in high-level languages, e.g., C or assembly. At the core of executing such programs in ZK is the repeated evaluation of a CPU step, achieved by branching over the CPU's instruction set. This approach is general and covers traversal-execution of a program's control flow graph (CFG): here CPU instructions are straight-line program fragments (of various sizes) associated with the CFG nodes. This highlights the usefulness of ZK CPUs with a large number of instructions of varying sizes.
Yibin Yang 0001, David Heath 0001, Carmit Hazay, Vladimir Kolesnikov, Muthuramakrishnan Venkitasubramaniam
CCS1
2024 Toward Malicious Constant-Rate 2PC via Arithmetic Garbling
Carmit Hazay, Yibin Yang 0001
EUROCRYPT (5)2
2024 Two Shuffles Make a RAM: Improved Constant Overhead Zero Knowledge RAM
Yibin Yang 0001, David Heath 0001
USENIX Security Symposium1
2023 Just How Fair is an Unreactive World?
Srinivasan Raghuraman, Yibin Yang 0001
ASIACRYPT (6)2
2023 Batchman and Robin: Batched and Non-batched Branching for Interactive ZK
abstract
Vector Oblivious Linear Evaluation (VOLE) supports fast and scalable interactive Zero-Knowledge (ZK) proofs. Despite recent improvements to VOLE-based ZK, compiling proof statements to a control-flow oblivious form (e.g., a circuit) continues to lead to expensive proofs. One useful setting where this inefficiency stands out is when the statement is a disjunction of clauses \mathcalL _1 łor \cdots łor \mathcalL _B. Typically, ZK requires paying the price to handle all B branches. Prior works have shown how to avoid this price in communication, but not in computation.
Yibin Yang 0001, David Heath 0001, Carmit Hazay, Vladimir Kolesnikov, Muthuramakrishnan Venkitasubramaniam
CCS1
2023 Towards Generic MPC Compilers via Variable Instruction Set Architectures (VISAs)
abstract
In MPC, we usually represent programs as circuits. This is a poor fit for programs that use complex control flow, as it is costly to compile control flow to circuits. This motivated prior work to emulate CPUs inside MPC. Emulated CPUs can run complex programs, but they introduce high overhead due to the need to evaluate not just the program, but also the machinery of the CPU, including fetching, decoding, and executing instructions, accessing RAM, etc.
Yibin Yang 0001, Stanislav Peceny, David Heath 0001, Vladimir Kolesnikov
CCS1
2022 EZEE: Epoch Parallel Zero Knowledge for ANSI C
abstract
Recent work has produced interactive Zero Knowledge (ZK) proof systems that can express proofs as arbitrary C programs (Heath et al., 2021, henceforth referred to as ZEE); these programs can be executed by a simulated ZK processor that runs in the 10KHz range. In this work, we demonstrate that such proof systems are amenable to high degrees of parallelism. Our epoch parallelism-based approach allows the prover and verifier to divide the ZK proof into pieces such that each piece can be executed on a different machine. These proof snippets can then be glued together, and the glued parallel proofs are equivalent to the original sequential proof. We implemented and we experimentally evaluate an epoch parallel version of the ZEE proof system. By running the prover and verifier each across 31 2-core machines, we achieve a ZK processor that runs at up to 394KHz. This allowed us to run a benchmark involving the Linux program bzip2, which would have required at least 11 days with the former ZEE system, in only 8.5 hours.
Yibin Yang 0001, David Heath 0001, Vladimir Kolesnikov, David Devecsery
EuroS&P1
2021 Zero Knowledge for Everything and Everyone: Fast ZK Processor with Cached ORAM for ANSI C Programs
abstract
We build a complete and efficient ZK toolchain that handles proof statements encoded as arbitrary ANSI C programs.Zero-Knowledge (ZK) proofs are foundational in cryptography. Recent ZK research has focused intensely on non-interactive proofs of small statements, useful in blockchain scenarios. We instead target large statements that are useful, e.g., in proving properties of programs.Recent work (Heath and Kolesnikov, CCS 2020 [HK20a]) designed an efficient proof-of-concept ZK machine (ZKM). Their machine executes arbitrary programs over a minimal instruction set, authenticating in ZK the program execution. In this work, we significantly extend this research thrust, both in terms of efficiency and generality. Our contributions include:• A rich and performance-oriented architecture for representing arbitrary ZK proofs as programs.• A complete compiler toolchain providing full support for ANSI C95 programs. We ran off-the-shelf buggy versions of the Linux programs sed and gzip, proving in ZK that each program has a bug. To our knowledge, this is the first ZK system capable of executing standard Linux programs.• Improved ZK oblivious RAM (ORAM). [HK20a] introduced an efficient ZK-specific ORAM BubbleRAM that consumes O(log2n) communication per access. We extend BubbleRAM with multi-level caching, decreasing communication to O(log n) per access. This introduces the possibility of a cache miss, which we handle cheaply. Our experiments show that cache misses are rare; in isolation, i.e., ignoring other processor costs, BubbleCache improves communication over BubbleRAM by more than 8×. Using BubbleCache improves our processor’s total communication (including costs of cache misses) by ≈ 25-30%.• Numerous low-level optimizations, resulting in a CPU that is both more expressive and ≈ 5.5× faster than [HK20a]’s.• Attention to user experience. Our engineer-facing ZK instrumentation and extensions are minimal and easy to use.Put together, our system is efficient and general, and can run many standard Linux programs. The resultant machine runs at up to 11KHz on a 1Gbps LAN and supports MBs of RAM.
David Heath 0001, Yibin Yang 0001, David Devecsery, Vladimir Kolesnikov
SP2
2017 LUTOSAP: Lookup Table Based Online Sample Preparation in Microfluidic Biochips
abstract
Existing sample preparation algorithms are either based on NP-style problem formulations, e.g., using integer linear programming (ILP), which runs very slowly, or based on heuristic algorithms, which cannot obtain optimal solutions regarding different objectives. This paper proposes the first online sample preparation algorithm based on the lookup table method, named LUTOSAP. LUTOSAP enables fast query response for online sample preparation requirements with the solution where the weighted sum of sample consumption, buffer consumption, and the number of mix-split operations is optimized. Experimental results show that LUTOSAP obtains optimal sample preparation solutions in microseconds within the accuracy tolerance of $0.2\%$ for both single and double concentration values, which is orders of magnitude faster than existing algorithms. For multiple concentration values, the multiple-target sample preparation algorithm in LUTOSAP obtains near-optimal solution based on the constructed lookup table in microseconds, which well meets the critical fast-response requirements in online sample preparation.
Lingxuan Shao, Yibin Yang 0001, Hailong Yao 0002, Tsung-Yi Ho, Yici Cai
ACM Great Lakes Symposium on VLSI2