Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Samuel A. Fineberg

dblp:75/5637 · also Sam Fineberg · DBLP profile ↗
← Back
11ranked-venue papers
7as first author
0since 2021 · last 2015
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 10 · 6 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Storage systems · 57% Parallel and multicore computing · 31% Distributed systems · 8%

Topics — the 11 heaviest of 12, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems › file systems
distributed file system
0.212015
Mantle: a programmable metadata load balancer for the ceph file system · SC 2015
Parallel and multicore computing
load balancing
0.212015
Mantle: a programmable metadata load balancer for the ceph file system · SC 2015
Storage systems
metadata management
0.212015
Mantle: a programmable metadata load balancer for the ceph file system · SC 2015
Parallel and multicore computing › multiprocessor system
distributed-memory multiprocessor
0.011992
Seamless - a latency-tolerant RISC-based multiprocessor architecture · ISCA 1992
Processor architecture and microarchitecture
multiprocessor architecture
0.011992
Seamless - a latency-tolerant RISC-based multiprocessor architecture · ISCA 1992
Processor architecture and microarchitecture › instruction set architecture › RISC
RISC processor
0.011992
Seamless - a latency-tolerant RISC-based multiprocessor architecture · ISCA 1992
Performance modeling and evaluation
benchmarking
0.011990
Experimental analysis of communication/data-conditional aspects of a mixed-mode parallel architecture via synthetic computations · SC 1990
Parallel and multicore computing
parallel architecture
0.011990
Experimental analysis of communication/data-conditional aspects of a mixed-mode parallel architecture via synthetic computations · SC 1990
Memory systems
data locality
0.011992
Seamless - a latency-tolerant RISC-based multiprocessor architecture · ISCA 1992
Parallel and multicore computing
programming models
0.011992
Seamless - a latency-tolerant RISC-based multiprocessor architecture · ISCA 1992
Parallel and multicore computing
parallel programming models
0.011990
Experimental analysis of communication/data-conditional aspects of a mixed-mode parallel architecture via synthetic computations · SC 1990

Methods — techniques the papers use, named apart from their topics

locality manager · 0.0data movement · 0.0timing measurement · 0.0synthetic algorithm coding · 0.0
YearPublicationVenuePosition
2015 Mantle: a programmable metadata load balancer for the ceph file system
abstract
Migrating resources is a useful tool for balancing load in a distributed system, but it is difficult to determine when to move resources, where to move resources, and how much of them to move. We look at resource migration for file system metadata and show how CephFS's dynamic subtree partitioning approach can exploit varying degrees of locality and balance because it can partition the namespace into variable sized units. Unfortunately, the current metadata balancer is complicated and difficult to control because it struggles to address many of the general resource migration challenges inherent to the metadata management problem. To help decouple policy from mechanism, we introduce a programmable storage system that lets the designer inject custom balancing logic. We show the flexibility and transparency of this approach by replicating the strategy of a state-of-the-art metadata balancer and conclude by comparing this strategy to other custom balancers on the same system.
Michael Sevilla, Noah Watkins, Carlos Maltzahn, Ike Nassi, Scott A. Brandt, Sage A. Weil, Greg Farnum, Samuel A. Fineberg
SC8
2011 Towards SIRF: self-contained information retention format
abstract
Many organizations are now required to preserve and maintain access to large volumes of digital content for dozens of years. There is a need for preservation systems and processes to support such long-term retention requirements and enable the usability of those digital objects in the distant future, regardless of changes in technologies and designated communities. A key component in such preservation systems is the storage subsystem where the digital objects are located for most of their lifecycle. We describe SIRF (Self-contained Information Retention Format) -- a logical storage container format specialized for long term retention. SIRF includes a set of digital preservation objects and a catalog with metadata related to the entire contents of the container as well as to the individual objects and their interrelationship. SIRF is being developed by the Storage Networking Industry Association (SNIA) with the intention of creating a standardized vendor-neutral storage format that will be interpretable by future preservation systems and that will simplify and reduce the costs of digital preservation.
Simona Rabinovici-Cohen, Mary G. Baker, Roger Cummings, Samuel A. Fineberg, John M. Marberg
SYSTOR4
2004 Fast and Flexible Persistence: The Magic Potion for Fault-Tolerance, Scalability and Performance in Online Data Stores
abstract
Summary form only given. We examine the architecture of computer systems designed to update, integrate and serve enterprise information. Our analysis of their scale, performance, availability and data integrity draws attention to the so-called 'storage gap'. We propose 'persistent memory' as the technology to bridge that gap. Its impact is demonstrated using practical business information processing scenarios. We conclude with a discussion of our prototype, the results achieved, and the challenges that lie ahead.
Pankaj Mehra, Samuel A. Fineberg
IPDPS2
1992 A Preliminary Performance Evaluation of the Seamless Parallel Processing System Architecture
Samuel A. Fineberg, Thomas L. Casavant
ICPP (1)1
1992 Seamless - a latency-tolerant RISC-based multiprocessor architecture
abstract
The Seamless parallel system being developed at the University of Iowa ECE Department provides a method for providing latency tolerance in physically-distributed memory systems utilizing “off-the-shelf” RISC CPU's without incurring the overhead of multithreading. Seamless encompasses an evolutionary new programming model emphasizing data locality that views communication as data movement rather than message passing I/O. A hardware Locality Manager is added to each processing element to perform this data movement concurrently with computation.
Samuel A. Fineberg, Thomas L. Casavant, Brent H. Pease
ISCA1
1991 Experimental Analysis of a Mixed-Mode Parallel Architecture Using Bitonic Sequence Sorting
Samuel A. Fineberg, Thomas L. Casavant, Howard Jay Siegel
J. Parallel Distributed Comput.1
1990 Experimental Analysis of a Mixed-Mode Parallel Architecture Performing Sequence Sorting
Samuel A. Fineberg, Thomas L. Casavant, Howard Jay Siegel
ICPP (3)1
1990 Experimental analysis of communication/data-conditional aspects of a mixed-mode parallel architecture via synthetic computations
abstract
Experimentation aimed at determining the potential benefit of mixed-mode SIMD/MIMD (single instruction, multiple data/multiple instruction, multiple data) parallel architectures is reported. The experimentation is based on timing measurements made on the PASM (Partitionable SIMD/MIMD) system prototype utilizing carefully coded synthetic variations of a well-known algorithm. The synthetic algorithms used to measure and evaluate this system were based on bitonic sorting of sequences stored in the processing elements. This computation was mapped to both the hybrids of the SIMD and MIMD modes. The computations were coded in these four ways and experiments were performed that explore the tradeoffs among them. The results of these experiments are presented and discussed, with special consideration of the effects of the system's architecture. The goal is to obtain implementation-independent analyses of the attributes of mixed-mode parallel processing with respect to the computational characteristics of the application being examined.>
Samuel A. Fineberg, Thomas L. Casavant, Howard Jay Siegel
SC1
1990 A Tool to Aid in the Design, Implementation, and Understanding of Matrix Algorithms for Parallel Processors
Jack J. Dongarra, Orlie Brewer, James Arthur Kohl, Samuel A. Fineberg
J. Parallel Distributed Comput.4
1988 Experimentally based parallel architecture evaluation
abstract
A technique for architectural evaluation that has been used with good results and that is applicable to most experimental and commercial machines is proposed. This technique is that of careful experimentation on a bare system, i.e. one without a resident kernel, operating system, or high-level language support. The experimentation involves the implementation of simple algorithms designed to utilize the basic features of the architecture and exploit its unique features. This technique makes possible the analysis of an architecture without the complexities introduced by most operating systems and compilers and can yield insight beneficial in future language, compiler, operating system, application, and system design. Hybrid SIMD/MIMD architectures are considered as an example.>
Samuel A. Fineberg
COMPSAC1
1988 Non-Deterministic Instruction Time Experiments on the PASM System Prototype
Samuel A. Fineberg, Thomas L. Casavant, Thomas Schwederski, Howard Jay Siegel
ICPP (1)1