The aim of this paper is to propose a real time reconfigurable (RTR) micro-FPGA using new non volatile memory. Magnetic tunneling junctions (MTJ) used in Magnetic random access memories (MRAM) are compatible with classical CMOS processes. Moreover remanent property of such a memory could limit configuration time and power consumption required at each power up of the die. Nevertheless, each configuration memory point has to be readable independently from each other, that is why the approach is different from the classical memory array one.

When designing a SoC, matching the required performances both in terms of processing power and power consumption tends to become more and more challenging. Moreover, since the range of targeted applications for every single product is widening rapidly, employing reconfigurable accelerators makes more and more sense to this purpose. Coarse grain reconfigurable architectures bring an alternative providing interesting performances / flexibility trade-offs over traditional approaches. This work presents an original method allowing to efficiently exploiting dynamically parallelism at both loop-level and task-level, which remains rarely used. This method called DHM (Dynamic Hardware Multiplexing) is based upon the use of a hardwired controller dedicated to the dynamical unroll of loops or scheduling of tasks. This work shows that significant performance improvements can be achieved through combining both intra and inter-task parallelism. Principles and validations are exposed through a case study on a coarse grain reconfigurable architecture, called Systolic Ring. The exposed method could be applied to any coarse and fine grain architectures.

The authors addressed the multi-tasking issue for reconfigurable coprocessors in random application contexts. A scheduling algorithm was proposed to handle simultaneously a set of random tasks and able to maximize the resource usage even when the task-load is low. For this, processes are considered as relocatable: a simple transformation scheme is applied by a configuration controller to the initial configuration in order to relocate or duplicate the task when necessary. In this paper, the proposed method is implemented on a coarse grain reconfigurable architecture with 8 and 32 processing elements. A large amount of random scenario have been simulated and the statistical results presented here clearly show real advantages of the proposed method, but also some limitations drawing the line of future works.

Emergent technologies such as magnetic tunneling junction (MTJ), used in MRAM design are compatible with CMOS conventional processes and can be used in configurable circuits. This type of memory seems to be interesting for programmable applications in order to limit configuration time and power consumption required at each power up of the device. FPGA configuration memory is distributed all over the device and each point has to be readable independently from each other, that is why the approach is different from the classical memory array one. In this paper a first FPGA architecture based on MTJ-SRAM cells is described.

New parallel execution based machine paradigms must be considered. Thanks to their high level of flexibility structurally programmable architectures are potentially interesting candidates to overcome classical CPUs limitations. Based on a parallel execution model, we present in this paper a new dynamically reconfigurable architecture, dedicated to data oriented applications acceleration. Principles, realizations and comparative results will be exposed for some classical applications, targeted on different architectures.

Presents a functional level built-in self-test of digital filters. This BIST technique is based on predetermined patterns which are not dependent on the filter implementation. Many examples show that stuck-at fault coverage is about 98%.>

It is demonstrated that a floating gate transistor (FGT) is influenced by its topological environment. The equivalent gate-to-source voltage of the FGT depends on the initial charges trapped in the gate oxide, the surrounding potential of metal lines and the drain-to-source voltage of the FGT itself. An electrical study of the floating gate fault is presented. A theoretical model taking into account the influence of the transistor's environment is proposed. Analytical expressions for the equivalent gate-to-source voltage are derived, and the FGTs electrical operation mode is analyzed. This model is validated by SPICE simulations and by actual device measurements. The problem of testing for FGTs is discussed.>