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Takenobu Shimizugashira

dblp:75/624 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 1998
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA architecture		 0.011998
A New FPGA Architecture for High-Performance bit-Serial Pipeline Datapath (Abstract) · FPGA 1998
Reconfigurable computing and FPGAs › FPGA implementation
FPGA datapath design		 0.011998
A New FPGA Architecture for High-Performance bit-Serial Pipeline Datapath (Abstract) · FPGA 1998
YearPublicationVenuePosition
1998 FPGA for High-Performance Bit-Serial Pipeline Datapath
abstract
In this paper, we introduce our work on the chip design of a new FPGA chip for high-performance bit-serial pipeline datapath which is customized both in the logic architecture and routing architecture. The chip consists of 200k transistors on 3.5 mm square substrate (excluding the IO pad area) using 0.5 /spl mu/ 2-metal process technology. The estimated clock frequency is 156 MHz.
Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda
 ASP-DAC2
1998 A New FPGA Architecture for High-Performance bit-Serial Pipeline Datapath (Abstract)
abstract
No abstract available.
Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda
 FPGA2
1997 High speed bit-serial parallel processing on array architecture
abstract
Word-parallel bit-serial processing is a solution to high speed processing suitable for VLSI. In this paper a new bit-serial parallel processing architecture is proposed. A VLSI chip for a digital filter is designed based on the proposed architecture and it is implemented on a gate array chip. Through the implementation, it is verified that bit-serial parallel processing on an array architecture achieves high speed processing and easy design.
Kazuhito Ito, Takenobu Shimizugashira, Hiroaki Kunieda
 ASP-DAC2