Developers have access to a wide range of storage APIs and functionality in large-scale systems, such as relational databases, key-value stores, and namespaces. However, this diversity comes at a cost: each API is implemented by a complex distributed system that is difficult to develop and operate. Delos amortizes this cost by enabling different APIs on a shared codebase and operational platform. The primary innovation in Delos is a log-structured protocol: a fine-grained replicated state machine executing above a shared log that can be layered into reusable protocol stacks under different databases. We built and deployed two production databases using Delos at Facebook, creating nine different log-structured protocols in the process. We show via experiments and production data that log-structured protocols impose low overhead, while allowing optimizations that can improve latency by up to 100X (e.g., via leasing) and throughput by up to 2X (e.g., via batching).

Wirelength is one of the most important metrics in the placement problem. Minimizing wirelength is not only beneficial, but also a fundamental step to optimize other metrics, such as timing, power, and routability. In this paper, we propose a high performance mixed-size wirelengh-driven placer called POLAR. POLAR is based on the recent popular look-ahead legalization idea. The goals of our look-ahead legalization are: 1) to achieve a roughly legalized placement and 2) to maintain cells' relative positions of quadratic placement while minimizing cell movements. To achieve these goals, in POLAR, look-ahead legalization is realized in a simple and elegant manner. Firstly, all placement density hotspots (where placement overflow occurs) are detected. Secondly, for each hotspot, an appropriate window is searched to cover it by enumerating many feasible candidates. Finally, cell-to-bin assignment is performed within each window by a fast recursive bisection method. The experimental results verify the efficiency of POLAR over the ISPD 2005 and 2006 benchmarks.

Timing closure, which is to meet the design's timing constraints, is a key problem in the physical design flow. During the timing optimization process, buffers can be used to speedup the circuit or serve as delay elements. In this paper, we study the hold-violation removal problem for today's industrial designs. Discrete buffers, accurate timing models/analysis, and complex timing constraints make the problem difficult and time-consuming to solve. In this paper, we first present a linear programming-based methodology to model the setup and hold-time constraints. Then based on the solution to the linear programming, buffers are inserted as delay elements to solve hold violations. In the experiment, our approach is tested on industrial designs, then runs with the industrial optimization flow, and better results in terms of hold violations and runtime are reported.

A new quadratic global placer called POLAR is proposed. POLAR is based on novel techniques for rough legalization and wirelength refinement. During look-ahead rough legalization (LAL), relative positions of cells are maintained as they are relocated with minimal displacement to relieve excess area density. For each “hotspot” where placement overfill occurs, an expansion region covering the hotspot is constructed. Then the movable cells within each of these expansion regions are evenly assigned to density bins inside the expansion region by displacement-minimizing recursive bisection. In addition, a fast density-preserving and wirelength-reducing discrete refinement is applied to the first few LAL placements before each of these is used to augment the quadratic model used to obtain the next major placement iteration. The experimental results show that POLAR outperforms the state-of-the-art academic placers over the ISPD 2005 benchmarks.