An especially daunting challenge of scheduling real-time applications on multiprocessor system on chip (MPSoC) is to incorporate timing anomalies due to access contention to shared resources. Time division multiplex arbitration (TDMA) provides static timing guarantees at the cost of significant loss in the average case performance of the application. This paper presents a shared resource contention arbitration approach allowing high bus utilization while guaranteeing WCET values for all tasks in the real-time application. The paper includes performance results obtained by executing hard real-time applications on a MPSoC with shared memory connected to the processors via a shared bus, implemented on a FPGA. The results show that the proposed approach provides: 1 bus bandwidth utilization close to static priority based arbitration, 2 a fairer bandwidth distribution compared to round robin arbitration, and 3 latency guarantees identical to TDMA.

Scalability and performance in multicore processors for embedded and real-time systems usually don't go well each with the other. Networks on Chip (NoCs) provide scalable execution platforms suitable for such kind of embedded systems. This article presents a NoC-based Heterogeneous Multi-Processor system, called NoC-HMP, which is a scalable platform for embedded systems developed in the GALS language SystemJ. NoC-HMP uses a time-predictable TDMA-MIN NoC to guarantee latencies and communication time between the two types of time-predictable cores and can be customized for a specific performance goal through the execution strategy and scheduling of SystemJ program deployed across multiple cores. Examples of different execution strategies are introduced, explored and analyzed via measurements. The number of used cores can be minimized to achieve the target performance of the application. TDMA-MIN allows easy extensions of NoC-HMP with other cores or IP blocks. Experiments show a significant improvement of performance over a single core system and demonstrate how the addition of cores affects the performance of the designed system.

The paper introduces a new multi-core SoC platform designed for industrial automation applications with mixed criticality. The applications are written in SystemJ language. The multi-core platform consisting of three different types of cores is implemented in a SoC that contains a standard dual-core ARM and a FPGA, which is used to run the critical part of the system. The platform is fully customizable in terms of number and types of cores to the needs of the application. An industrial automation case study is used to demonstrate the use and performance of the multi-core SoC.

In this paper we present an approach to efficiently mix Java with asynchronous and synchronous concurrency and execute it on a specialized Java processor extended with capabilities for concurrency and reactivity. A new processor, which uses JOP (Java Optimized Processor) as its base, executes concurrent programs that comply with Globally Asynchronous Locally Synchronous (GALS) formal model of computation by clearly distinguishing between concurrency and reactivity control flow and Java control flow. The new processor, called JOP-Plus, can be used for embedded and even real-time applications in which majority of code is written in Java and the overall programs specified and structured in SystemJ system-level concurrent programming language.

This paper presents a novel, high performance and low cost execution architecture for the system level GALS programming language SystemJ, which extends Java with synchronous reactive features present in Esterel and asynchronous constructs of CSP (Communicating Sequential Processes). The new architecture is based on JOP (Java Optimized Processor), which is a hardware implementation of the Java Virtual Machine (JVM). The JOP, inherently suited to data-driven transformational operations, is extended to efficiently execute the control constructs and control flow of SystemJ. The new core, which is called RJOP (Reactive JOP) supports efficient execution of both data dominated and control dominated embedded applications. It also maintains the time-predictable execution of the applications intended for real-time embedded systems and calculation of Worst Case Reaction Time (WCRT) as provided by the original core. The initial results indicate significant performance improvement and lower resource requirements over the existing architectures used for the SystemJ execution.

This paper presents GALS-JOP processor for efficient execution of programs written in SystemJ GALS programming language, which extends Java with both synchronous and asynchronous concurrency and directly supports the design of concurrent and reactive programs that comply with globally asynchronous locally synchronous (GALS) formal model of computation (MoC). In the first step, a Java optimized processor (JOP) is enhanced with a control processor (CP), which deals with concurrency and reactivity, to design an intermediate solution, called tandem processor, or TP-JOP, in which control processor and JOP work together to implement control flow and data operations of GALS programs, respectively. Then, JOP and the CP functionalities are merged into a single processor, GALS-JOP, which enriches JOP with some key constructs and abstractions for efficient implementation of SystemJ GALS programs. Experimental results demonstrate superiority of the new processor over all other approaches for implementation of SystemJ programs so far making it suitable for embedded systems.