The high performance requirements of networking applications has led to the advent of programmable network processor (NP) architectures that incorporate symmetric multiprocessing, and block multi-threading. The paper presents an automated system-level design technique for process mapping on such architectures with an objective of maximizing the worst case throughput of the application. As this mapping must be done in the presence of resource (processors and code size) constraints, this is an NP-complete problem (Ausiello et al., 1999). We present a polynomial time approximation algorithm guaranteed to generate solutions with throughput at least 1/2 that of optimal solutions. The proposed algorithm was utilized to map realistic applications on the Intel IXP2400 (NP) architecture, and produced solutions within 78% of optimal.

Network processor architectures incorporate block multi-threading to alleviate the performance degradation due to memory access latencies. Application design on such architectures requires the determination of the number of threads, and mapping of data items to the various memory elements such that the overall throughput is maximized. The paper presents a quasi-polynomial time approximation algorithm for the multi-threading aware data mapping problem which can be shown to be NP complete. The algorithm generates solutions with throughput no less than 1 / 2(1+ε) of optimal and data memory requirements no more than (1 + ε) times the memory constraints. Experimental results obtained by mapping applications on the Intel IXP 2400 network processor demonstrate that the algorithm is able to generate solutions whose throughput is within 80% of the optimal when ε = 0.5.

Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to support the high performance requirements of networking applications. The paper presents an automated system-level design technique for application development on such architectures. The technique incorporates process transformations and block multi-threading aware data mapping to maximize the worst case throughput of the application. We propose integer linear programming formulations for process allocation and data mapping on SMP and block multi-threading based network processors. The paper presents experimental results that evaluate the technique by implementing representative network processing applications on the Intel IXP 2400 architecture. The results demonstrate that our technique is able to generate high-quality mappings of realistic applications on the target architecture within a short time

Network processors incorporate several architectural features, including symmetric multiprocessing (SMP), block multithreading, and multiple memory elements, to support the high-performance requirements of current day applications. This article presents automated system-level design techniques for application development on such architectures. We propose integer linear programming formulations and heuristic techniques for process allocation and data mapping on SMP and block-multithreading-based network processors. The techniques incorporate process transformations and multithreading-aware data mapping to maximize the throughput of the application. The article presents experimental results that evaluate the techniques by implementing network processing applications on the Intel IXP 2400 architecture.