In this paper, an analog front-end (AFE) local-field potential (LFP) acquisition unit with real-time stimulation artifact removal is proposed and verified for closed-loop deep brain stimulation (DBS) applications. The proposed acquisition unit is called the synchronized sample-and-hold stimulation artifact blanking (SSAB) AFE LFP acquisition unit. Both right-leg-driven (RLD) circuit and monopolar electrode-tissue impedance (ETI) measurement circuit associated with the AFE amplifier are also proposed. During closed-loop stimulations, the artifact removal is realized through the SSAB-IPC by blanking the AR-CCIA with a clock synchronized to the stimulation-enable signal and holding the amplifier at its state before stimulation through a sample-and-hold operation. After stimulation, the acquisition unit can quickly recover from the holding state back to the LFP recording state to reduce the discontinuity in LFP recording. The proposed acquisition unit was fabricated in 0.18-$\mu {\mathrm{ m}}$CMOS technology. With the RLD circuit, the measured CMRR is 124– 145 dB in the signal bandwidth. The fabricated monopolar ETI measurement circuit has a measurement error less than 8.3% with an extra power consumption of$2.65 \mu \text{W}$. The experimental results have shown that the proposed SSAB AFE LFP acquisition unit is feasible for the integration of SoCs in real-time closed-loop DBS systems for various applications.

This article presents and demonstrates the design of a high dynamic range (HDR) CMOS image sensor (CIS). Detailed operation of various comparator circuits is analyzed. A low-noise, area-efficient, wide-input range comparator is proposed for HDR applications. Based on the analysis, a six-transistor (6T) comparator is proposed with a p-type metal oxide semiconductor (PMOS) input triplet, which effectively increases the input range of a conventional PMOS-input type comparator and compensates the charge injection and kT/C noise introduced from pixels switching between high-conversion-gain (HCG) and low-conversion-gain (LCG) modes. The proposed scheme achieves an extra high dynamic range (DR). A full HD ($1920\times1080$) HDR image sensor with$2.9 ~\mu \text{m}$pixel pitches is fabricated in a 55 nm one-ploy five-metal (1P5M) CIS process. The incorporated analog-to-digital conversion (ADC) demonstrates a 12-bit resolution, a noise of$96 ~\mu _{\mathrm {VRMS}}$, a power consumption of$25 ~\mu \text{W}$, an area of$2.9\times 400\,\,\mu \text{m}$, and its integral non-linearity (INL) and differential non-linearity (DNL) are −0.43/+7.22 and −0.30/+0.29 LSB, respectively. The sensor achieves a 120-dB DR at 30 frames/sec and a temporal noise of 0.91e-.

This paper presents a comprehensive analysis of hardware accelerators for neural networks in both the digital and time domains, where the latter includes spatially unrolled (SU) and recursive (REC) architectures. All accelerators are implemented and synthesized in a 65nm CMOS technology. An identical neural network model is implemented in the digital and time domain for comparative purposes in terms of throughput, power consumption, area, and energy efficiency. Post-synthesis results show that SU achieves the highest energy efficiency of 145 TOp/s/W with a throughput of 4 GOp/s. The digital core is the fastest among other cores, whereas REC is the slowest but is the most area-efficient, occupying 0.114 mm2. SU is more suited for applications with stringent power constraints and average performance, while REC is better suited for applications where the area is the most important requirement and the throughput is less significant. In contrast, the digital core is preferable for large neural networks and critical applications that require high performance.

This paper investigates power MOSFET stress strategies for both package and chip aging evaluation. Two stress test methods are developed to speed up packaging and chip aging process respectively. As a result, the characteristics shifts of package and chip aging can be plotted independently. Thus, the measurement accuracy and measurement time can be improved. A test chip is designed and fabricated in a 0.15μm BCD process. The measured results demonstrate a 10kμm power MOSFET has Ronincreased by 72% after 6.3hr stress for the package aging. For the chip aging, the MOSFET has Ronincreased by 12% after 600 times stress pulses. The measurement verifies that the accelerated aging in the package and the chip can be controlled separately.

This brief proposes a glitch reduction approach by dynamic capacitance compensation of binary-weighted current switches in a current-steering digital-to-analog converter (DAC). The method was proved successfully by a 10-bit 400-MHz pure binary-weighted current-steering DAC with a minimum number of retiming latches. The experiment results yield very low-glitch energy during major carry transitions at output, which is <;1 pVs. This brief utilizes a layout structure to improve the spurious-free dynamic range at high signal frequencies. This chip was implemented in a standard 0.18-μm CMOS technology and consumes 20.7 mW at 400 MS/s.

This paper proposes a new architecture of 12-bit current-steering digital-to-analog converter (DAC) with novel biasing scheme. In the proposed DAC, two 6-bit binary-weighted current source arrays are designed with two reference currents. The technique allows significant area savings without impairing static accuracy. The paper also presents a method to generate dual reference currents, whose design is compact and consumes low static power. The active area of the 12-bit DAC is 0.36mm2approximately. This chip was fabricated by a standard 0.18μm CMOS technology, and consumes 38mW at 180MS/s update rate with 1.8V supply voltage.

This paper presents a dual-level dual-phase pulse-width modulation (DLDP PWM) Class-D audio amplifier circuit which enhance amplifier linearity and reduce distortion. The proposed DLDP PWM Class-D audio amplifier includes two sets of non-overlapping triangular waves, each at its respectful offset levels. Each set of triangular waves is composed of two 180° out-of-phase triangular waves. The differential power stage consists of 8 power transistors, with voltage swings up to +/- 6V. Simulated results shows that the proposed DLDP PWM Class-D audio amplifier features an SNR up to 105 dB, and the THD is suppressed below 0.001 %, with the 3rd harmonic below -102 dBV.

This paper presents a low phase-noise phase locked loop (PLL) system with a Multi-Phase Over-Sampling Charge Pump (MPOSCP) for wireless applications. The low phase-noise frequency synthesizer reduces ripples and noise on the control voltage of the ring voltage-controlled oscillator (VCO) as a means to control in-band noise at the output of the PLL. An MPOSCP is proposed to perform multi-phase over-sampling control for the charge pump (CP) in locked state. The proposed frequency synthesizer was fabricated using the TSMC 90-nm CMOS process. The prototype occupies 0.046mm2active area, the reference frequency is 27 MHz, and the output frequency is 432 MHz with the total power consumption of 7 mW. The PLL achieved phase noise below -100 dBc/Hz from 15 Hz to 100 kHz with the reference spurs below-48 dBc.

This brief presents a low-dropout (LDO) voltage regulator without output capacitors that achieves fast transient responses by hybrid dynamic biasing. The hybrid dynamic biasing in the proposed transient improvement circuit is activated through capacitive coupling. The proposed circuit senses the LDO regulator output change so as to increase the bias current instantly. The proposed circuit was applied to an LDO regulator without output capacitors implemented in standard 0.35- μm CMOS technology. The device consumes only 25 μA of quiescent current with a dropout voltage of 180 mV. The proposed circuit reduces the output voltage spike of the LDO regulator to 80 mV when the output current is changed from 0 to 100 mA. The output voltage spike is reduced to 20 mV when the supply voltage varies between 1.3 and 2.3 V with a load current of 100 mA.

This brief presents a low-spur phase-locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator to reduce the reference spur at the output of the PLL. A novel random clock generator is presented to perform the random selection of the phase frequency detector control for the charge pump in locked state. The proposed frequency synthesizer was fabricated in a TSMC 0.18-μm CMOS process. The proposed PLL achieved phase noise of -93 dBc/Hz with a 600-kHz offset frequency and reference spurs below -72 dBc.

This paper proposes an all-digital fast-locking pulsewidth-control circuit with programmable duty cycle. In comparison with prior state-of-the-art methods, our use of two delay lines and a time-to-digital detector allows the pulsewidth-control circuit to operate over a wide frequency range with fewer delay cells, while maintaining the same level of accuracy. This paper presents a new duty-cycle setting circuit that calculates the desired output duty cycle without the need for a look-up table. The circuit was fabricated under the two-stage matrix converter 0.18-CMOS process. Results show that the proposed circuit performs well for an input operating frequency ranging from 200 to 600 MHz, and an input duty cycle ranging from 30% to 70%. It achieves a programmable output duty cycle ranging from 31.25% to 68.75% in increments of 6.25%.

A continuous-time fourth-order equiripple linear phaseGm-Cfilter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined common-mode feedforward and common-mode feedback circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining an equivalent negative resistor circuit at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the deep-NWELL technology. The modified automatic tuning circuit relaxes the speed requirement of the tuning blocks. Through the use of the operational transconductance amplifier as a building block with the automatic tuning scheme, the filter - 3 dB cutoff frequency is 1 GHz with the group delay less than 4% variation up to 1.5 fc frequency. The - 43 dB of IM3 at filter cutoff frequency is obtained with -4 dbm two-tone signals. Implemented in 0.18-μ m CMOS process, the chip occupies 1 mm2and consumes 175 mW at a 1.5-V supply voltage.

This paper presents novel frequency compensation techniques for low-dropout (LDO) voltage regulator. An enhanced active feedback frequency compensation is employed to improve its frequency response. This LDO can provide high stability for loading current range up to 100 mA without loading capacitors. Moreover, the total compensation capacitors only require 7 pF for this technique. This allows us to integrate the compensation capacitors within the LDO chip easily. The proposed LDO regulator was designed using TSMC 0.35-mum CMOS technology. With an active area of 0.14 mm2, the quiescent current is only 40 muA. The input voltage is ranged from 1.73 V to 5 V for loading current of 100 mA and the output voltage of 1.5 V. The main advantage of this approach is that the LDO circuit can be stable when we connect external load capacitors with ultra low ESR, or even when we eliminate the load capacitors.

In this paper, a low power low-noise amplifier (LNA) using inductor-coupling resonated technique is designed for ultra-wideband (UWB) wireless system. The design consists of a wideband input impedance matching network, one stage cascode amplifier with inductor-coupling resonated load, and an output buffer; it was fabricated in TSMC 0.18 um standard RF CMOS process. The UWB LNA gives 10.8 dB power gain and 9.4 GHz 3 dB bandwidth (1.2 GHz - 10.6 GHz) while consuming only 6.2 mW through a 1.2 V supply, including output buffer. Over the 3.1 GHz - 10.6 GHz frequency band, a minimum noise figure of 3.9 dB and input return loss lower than -5.7 dB have been achieved.

A low power CMOS Voltage Reference Circuit was designed and implemented by TSMC 0.18-μm CMOS process. The voltage reference circuit uses the VGSdifference between two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient. The reference voltage can be obtained by combining the weighted VGSdifference with weak-inversion VGSvoltage, which has a negative temperature coefficient. This circuit provides a nominal reference voltage of 621 mV, a temperature coefficient of 11.5 ppm/°C in [-20°C~120°C] from a 1.5V supply voltage. The line regulation of the reference voltage is 6 mV/V when the supply voltage is increased from 1.5V to 3V. The chip area is 0.132 mm2and dissipates 17.25 μW at room temperature. By connecting a 0.22 μF loading capacitor, the measured noise density at 100 Hz and 100 kHz is 0.14 μV/√Hz and 22.2 μV/√Hz, respectively.

This paper presents a high linearity MOSFET-only transconductor based on differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. Transconductance tuning could be achieved by transistors operating in the linear region. The simulated total harmonic distortion (THD) under 1-V power supply voltage shows 12 dB improvement of the proposed version, and -65 dB THD can be achieved for a 1 MHz 700 mVppdifferential input. Monte-Carlo simulation over the corner variation and transistor mismatch guarantees the shown performance. The static power consumption is 130 μW. Simulation results demonstrate the agreement with theoretical analyses.

This paper proposes a high performance operational transconductance amplifier (OTA) which is based on the pseudo-differential architecture with addition of linearity improved circuits. The OTA is designed under low power supply voltage consideration while its gain, excess phase, and linearity are well maintained. A common-mode control system, including common-mode feedback (CMFB) and common-mode feedforward (CMFF) circuits, is added to ensure stability at high frequency. Results show that the topology can achieve the total harmonic distortion (THD) to the -56dB with 100MHz balanced differential input signals up to 300mVpp at 1-V supply voltage by the TSMC 0.18mum CMOS process. Its power consumption is 1.8mW

The design and performance of a rail-to-rail low-voltage CMOS fifth-order elliptic low-pass GM-C filter for baseband mobile communication are presented. The operational transconductance amplifier (OTA) used in this filter is a low-voltage rail-to-rail voltage-to-current converter (V-I converter). In this V-I converter, an N-type V-I converter cell is connected in parallel with its counterpart, a P-type V-I converter cell, to achieve common-mode (CM) rail-to-rail operation. Two maximum-current selecting circuits and an output current subtraction circuit are utilized to generate constant-g/sub m/ output currents for this OTA. This fifth-order elliptic low-pass GM-C filter operates at a supply voltage of 3 V and has a cutoff frequency of 280 to 405 kHz. It provides up to 700 mV/sub pp/ output with 1% total harmonic distortion (THD), dissipates 2.48 mW at V/sub cm/=1.5 V, and occupies 1.62 mm/sup 2/ in a 1.2-/spl mu/m CMOS technology.