Generating high-quality depth maps with accurate values is a critical research topic, and various depth estimation methods, such as Time-of-Flight (ToF) and Monocular Depth Estimation (MDE), are advancing rapidly. However, each single-sensor approach is inherently limited by the characteristics of its respective modality. Meanwhile, fused approaches using multiple sensors or dedicated trained models are often plagued by system complexity and limited generalization. In this paper, we propose an adaptive depth processing system based on the foundation transformer and ToF fusion, aiming to harness the precision of ToF data and the high-quality depth priors provided by the foundation model in a monocular and zero-shot manner. A hardware–algorithm co-design partitions the computation between a dedicated ASIC for compute-intensive foundation transformer acceleration and an MPSoC FPGA for potential reconfigurable fusion, yielding 36.4 ms latency and 1.9 W power under a 27.6 GOPS/frame workload. Zero-shot evaluations on various ToF data sources including FLAT, TICaM, and in-house captures confirm strong cross-domain generalization, demonstrating the system’s adaptability, efficiency, and accuracy.

Indirect time-of-flight (iToF) is one of the most straightforward approaches to capture 3D images. However, due to the nature of the iToF camera, it is still challenging to get reliable and accurate depth images from the raw data in the image signal processor (ISP) pipeline due to environmental issues. Previous iToF ISP works mainly focus on the traditional pipeline, such as filters and depth calculation. In this work, we present an end-to-end deep-learning-based iToF ISP. The proposed iToF ISP system can generate real-time depth images with deep-learning-based noise reduction and multipath interference (MPI) reduction. With the mixed-bit convolutional neural network (CNN) with 96.5 % sparsity and the mixed-bit sparse accelerator, the CNN is accelerated by 2.78× and negligible mean average error (MAE) loss has been achieved on the FLAT dataset using the proposed ISP pipeline.

A switched-capacitor dc-dc voltage regulator that converts an input of 2.4-3.6 V to an output of 30 V has been designed to power display driver integrated circuits. A novel Fibonacci structure, named connect-point-shift, is proposed to improve the current drivability, which increases the minimum current drivability from 0.16 to 0.274 mA. This scheme saves the chip size by approximately 40% while providing equal current drivability as the traditional one. The power efficiency has been improved by 1%-7%, and a peak efficiency of 83.4% has been achieved. The adaptive-conversion-ratio has been adopted for ripple and efficiency improvement. A pulse skip regulator and a linear regulator are utilized to keep the output terminal of the charge pump stable at around 30 V. Their ripple, efficiency, load regulation, and line regulation are compared for further optimization. Theories of Degenerate State and state-space averaging are applied to validate the performance enhancement. This scheme has been fabricated and validated by a 0.11-μm 1.5 V/6 V/30 V process.

An output-capacitor-free multi-stage low-dropout regulator (LDO) with new compensation scheme is presented. This scheme relieves the requirement of compensation capacitor to be 1.2pF by making use of the large gate capacitance of pass transistor as a large on-chip compensation capacitor. With this compensation scheme, the LDO can employ a multi-stage error amplifier for precise line and load regulation (total line and load error ≪ 0.04%) without sacrificing chip area and its bandwidth. Thus, recovery time of LDO is 1 μ s upon a step-load change in between 1mA and 100mA. Its output-capacitor-free nature and high area-efficiency make it particularly attractive for System-on-Chip (SoC) designs. Proposed LDO is fabricated in a 0.35μm standard CMOS technology and measurement results confirm with analysis and simulation results.

A CMOS-compatible one-time programmable (OTP) memory array for RFID applications is presented. Three zero-mask antifuse (AF) devices were evaluated on their feasibility for RFID applications. Among the AFs, the gate oxide AF device can be programmed using only 7 /spl mu/W of peak power and was chosen to form the RFID memory array. A memory array architecture is presented based on a compact 2-transistor cell, together with a programming circuit that does not require special high voltage transistors and consumes zero DC current during programming. The device structures were fabricated in 0.18 /spl mu/m process and were experimentally verified, while circuit simulations were performed using TSMC 0.18 /spl mu/m model on Cadence Analog Artist.

A micro-DNA-array based on integrated CMOS active pixel sensor (APS) technology is demonstrated. This system utilizes gold nano-particle binding to a DNA sample, which subsequently absorbed to the chip surface through the hybridization process when a matching between the DNA samples and DNA probes on the chip surface is found. The degree of DNA matching is reflected by the opacity of a certain location on the chip, which can be detected by the underlying CMOS APS array. The chip has been fabricated with a 0.5/spl mu/m CMOS process and contains on-chip timing control, dynamic range enhancement by pulse-width modulation and correlated sampling. The system can detect DNA sample with extremely low concentration under ordinary light source.

In this paper we report the fully depleted CMOS/SO1 device design guidelines for low power applications.Optimal technology, device and circuit parameters are discussed and compared with bulk CMOS based design.The differences and similarities are summarized.We believe this is the first such study to be reported.1.

The leakage current due to the parasitic PN junction diodes in SO1 DTMOS (Dynamic Threshold Voltage MOSFET) inverter is reported.The additional power dissipation in DTMOS inverter due to the diodes is quantified through an analytical model and verified by MEDIC1 simulation.Power dissipation between conventional SO1 CMOS and SO1 DTMOS inverters is compared.