In this work we present a technology for dynamically introducing fault structures into digital twins without the need to change the virtual prototype model. The injection is done at the beginning of a simulation by dynamically rewiring the involved netlists. During the simulation on a realtime platform, faults can be activated or deactivated triggered by sequences, statistical effects or by events from the real world. In some cases the fault structures can even be auto-generated directly from a formal specification, which further automates the development process for safety-relevant systems. The approach is demonstrated at a SystemC/ SystemC AMS virtual prototype of a safety-critical sub-systems which runs on a dSPACE real-time hardware.

Electromigration (EM) is becoming a progressively severe reliability challenge due to increased interconnect current densities. A shift from traditional (post-layout) EM verification to robust (pro-active) EM-aware design - where the circuit layout is designed with individual EM-robust solutions - is urgently needed. This tutorial will give an overview of EM and its effects on the reliability of present and future integrated circuits (ICs). We introduce the physical EM process and present its specific characteristics that can be affected during physical design. Examples of EM countermeasures which are applied in today's commercial design flows are presented. We show how to improve the EM-robustness of metallization patterns and we also consider mission profiles to obtain application-oriented current-density limits. The increasing interaction of EM with thermal migration is investigated as well. We conclude with a discussion of application examples to shift from the current post-layout EM verification towards an EM-aware physical design process. Its methodologies, such as EM-aware routing, increase the EM-robustness of the layout with the overall goal of reducing the negative impact of EM on the circuit's reliability.

Process variations and atomic-level fluctuations increasingly pose challenges to the design and analysis of integrated circuits by introducing variability. Although several approaches have been proposed to deal with the inherent statistical nature of circuit design, we consider them incomplete with two important aspects often being insufficiently addressed: 1) non-Gaussian distributions and 2) highly correlated parameters. To address these points, we propose a fully multivariate and non-Gaussian approach based on an arbitrary model. A subset of the model parameters is treated as a multidimensional random variable, which is represented by a combination of generalized lambda distributions and Spearman rank correlation matrices-a very general approach with nearly arbitrary freedom in distribution shapes and parameter correlations. In our application scenarios, we show that such a model is able to fully and accurately capture variability in device compact models and standard cell performance models. Finally, we present adapted analysis methods making use of these models in circuit simulations and in efficient gate level analyses of digital circuits with high accuracy.

Variability continues to pose challenges to integrated circuit design. With statistical static timing analysis and high-yield estimation methods, solutions to particular problems exist, but they do not allow a common view on performance variability including potentially correlated and non-Gaussian parameter distributions. In this paper, we present a probabilistic approach for variability modeling as an alternative: model parameters are treated as multi-dimensional random variables. Such a fully mul-tivariate statistical description formally accounts for correlations and non-Gaussian random components. Statistical characterization and model application are introduced for standard cells and gate-level digital circuits. Example analyses of circuitry in a 28 nm industrial technology illustrate the capabilities of our modeling approach.

Layout generation remains a critical bottleneck in analog circuit design. It is especially distracting when re-using an existing design for a similar specification or when transferring a working design to a new technology. This paper presents a new methodology for layout generation of analog circuits that is based on a modular circuit design and a so-called "executable design flow description". This is created once manually and allows to describe the layout in a technology independent and parameterizable manner assuring a consistent view of circuit and layout design. Complex layouts can be created in negligible time, achieving an early involvement of layout effects in the circuit design. Furthermore, the parameterization of the design description allows simplified technology transfer and seamless access to sizing tools.