We present VisAssist, the first large-scale video question-answering dataset with 13,413 real-world videos captured by visually impaired users, addressing a critical gap in assistive vision research. Unlike existing benchmarks relying on third-person footage, VisAssist provides authentic first-person perspectives that uniquely capture challenges in blind photography—including unconventional framing, motion artifacts, and frequent information omission. Benchmark evaluations of SOTA multimodal models reveal systematic limitations: severe deficiencies in spatial reasoning when processing dynamic first-person viewpoints, an inability to distinguish missing information from poor capture quality leading to hazardous hallucinations, and fragile text understanding especially for non-Latin scripts under suboptimal conditions. This work establishes a vital real-world benchmark and underscores the need for specialized architectures in visual assistance systems.

This paper presents a fully integrated NMOS stimulator using a hybrid dynamic bulk biasing technique (HDBT) and a charge-pump-like control technique (CCT) in a 180-nm bulk CMOS technology. HDBT integrates terminal-voltage-dependent and logic dynamic bulk biasing to set the bulk bias voltage according to the electrode voltage. CCT adds a DC voltage to the gate terminal through a diode and capacitor to help turn on the NMOS transistor. It helps turn off the transistor by shorting the source and gate terminals together and applying two diodes across the drain and source terminals. To achieve an electrode voltage higher than the breakdown voltage of substrate diode ($V_{\mathrm {BD}}$) with an independent power supply, a high voltage tolerant switch is proposed with HDBT and CCT. A high voltage interface is also proposed, utilizing the capacitor adaptive biasing, to overcome the limitation of$V_{\mathrm {BD}}$between the high and low voltage domains and to accommodate the variation of electrode voltage. Fabricated in a 180-nm standard CMOS technology, the stimulator achieves a maximum electrode voltage ($V_{\mathrm {E,MAX}}$) of 18.74V under a 3.3-V supply, with a highest$V_{\mathrm {E,MAX}}$/$V_{\mathrm {BD}}$ratio of 1.27 than state-of-the-art stimulators, including non-standard technology designs. In a continuous output test mode over 10million cycles, the variation of$V_{\mathrm {E,MAX}}$is less than 150mV. The measured maximum residual voltage on the capacitor is 13.55mV.

This paper presents a hybrid all-NMOS rectifier with two gate-biasing techniques to extend the power dynamic range (PDR) for wireless power transfer. The proposed hybrid rectifier combines the strengths of the cross-connected (CC) and diode-based (DB) configurations, achieving both a high forward current and a small reverse current along the PDR. Additionally, two separate gate-biasing techniques are employed to optimize the gate bias voltage for the gate-biased-CC and gate-biased-DB parts, respectively. All transistors in the rectifier are NMOS transistors, which can minimize the total area when extended to multi-stage configurations. The circuit is implemented in a 180-nm CMOS process, occupying an area of 0.195 mm2. Experimental results show a sensitivity of -10.3 dBm with a 1 MΩ load and a peak power conversion efficiency of 78.6% at -7.4 dBm with a 3 kΩ load. In addition, the proposed rectifier achieves a PDR greater than 22.3 dB with loads below 5 kΩ.

This paper presents a monopolar neural stimulator using dynamic current replication technique based on switched-capacitor sampling. It employs dynamic current mirror circuits as the current source and the current sink to overcome the impact of process variation on current matching, achieve good charge balance and ensure the security of the monopolar neural stimulator. The proposed monopolar stimulator is implemented with a 0.18-μm 1.8 V/3.3 V standard CMOS process. The simulated results indicate that the current mismatch between the cathodic and anodic current is less than 0.21%, and the charge mismatch is below 0.33% within the entire stimulus current range (0.3 mA ~ 3 mA). The corresponding maximum residual average DC current error with shorting electrode discharge is less than 1 nA.

This paper presents a self-powered parallel synchronized switch harvesting on inductor (P-SSHI) active rectifier with an energy-efficient adaptive switch control circuit. The energy-efficient adaptive switch control circuit reuses comparators within the active rectifier for both zero-crossing detection and voltage flipping detection, simplifying the switch control module. The proposed active rectifier incorporates an active diode and a MOSFET within each energy transfer path to mitigate the forward voltage drop across rectifying elements. The proposed P-SSHI circuit which includes a diode in each voltage flipping path shows high adaptability to different inductances. All the auxiliary circuits are powered by the storage capacitor. The proposed circuit is designed in 180 nm CMOS process, and the total occupied chip area is 0.18 mm2. The power dissipation of the switch control module is only 0.15 μW, owing to its simplicity. The simulation results show that the proposed design achieves a high voltage flipping efficiency of 85.4%. The maximum output power is 5.5 times greater than that of the ideal full-bridge rectifier.

This paper presents a fully integrated stimulator using a dynamic bulk biasing technique and a dynamic control scheme in a 180-nm bulk CMOS technology. Unlike the conventional bulk biasing method, the bulk bias voltage is dynamically set according to the different stimulation phases. It avoids the underlying leakage current paths, and improves the maximum stimulation voltage compliance (MSVC). Together with dynamic bulk biasing scheme, a high voltage interface is designed to overcome the limitation of the breakdown voltage of the substrate diode ( V$_{\mathbf{BD}}$) between the high and low voltage domains. An all-NMOS dynamic charge pump is also proposed as a dynamic power supply above V$_{\mathbf{BD}}$and provides dynamic bulk-biasing voltages. Fabricated in a 180-nm standard CMOS technology, the stimulator achieves an MSVC of$\pm$16.5 V under a 3.3-V supply, and the achieved MSVC is$\sim$1.11 times higher than the V$_{\mathbf{BD}}$($\sim$14.8 V) of the substrate diode. The stimulator is also measured in a continuous output test mode for over 10 million cycles, the variation of$\vert$MSVC$\vert$is less than 200 mV.

Recently, infrared thermal radiation effect correction methods are dominated by removing bias field in spatial domain. Since they do not consider the low-frequency characteristics of thermal radiation bias field and the high-frequency information of image content, these methods often fail in the enhancement of contrast and details. To address this problem, we propose a novel wavelet decomposition two-stage network for infrared thermal radiation effect correction, named WDTSNet. Through wavelet decomposition, we construct a low-frequency thermal radiation effect coarse correction subnetwork (LFCCSN) and a high-frequency detail enhancement fine correction subnetwork (HFFCSN), respectively. Firstly, we take the small size low-frequency component of the degraded image after discrete wavelet transformation (DWT) as the input of the first stage LFCCSN and propose an intra-block multiscale residual dense module (IMRDM) to complete the coarse correction and contrast enhancement through different scales of receptive fields and intra-block channel information interaction. Secondly, we perform inverse discrete wavelet transformation (IDWT) to obtain the input of the second stage HFFCSN, and build a high-frequency gated residual module (HGRM) in HFFCSN to remove residual thermal radiation bias field and acquire the enhanced high-frequency information. In addition, we further design dual-branch cross-scale attention fusion module (DCAFM) between encoders and decoders to effectively aggregate the cross-scale information flow. Extensive experiments on simulated and real infrared images demonstrate that the proposed WDTSNet performs well on enhancing contrast and details than existing methods. The code will be publicly available upon acceptance.

In this paper, a high global efficiency OOK transmitter (TX) working at 400–460 MHz is proposed by utilizing third-harmonic edge-combining technique for low power biomedical applications. The operation frequency of the proposed TX before the third-harmonic edge-combiner (THEC) is 1/15 of the output RF frequency and 1/3 of the traditional edge-combiner-based TX. The multi-phase signals used for edge combiner (EC) are generated by a delay-locked loop (DLL) at a relative low frequency, which significantly reduces the overall TX power consumption. The TX is designed in 55-nm CMOS process with a core area of 0.02 mm2, the proposed TX consumes a DC power of$98.75\ \mu\mathrm{W}$under a 0.8 V supply voltage. The simulated output power is −14 dBm with 20 Mbps OOK data. The TX achieves a 41% global efficiency and a 4.94 pJ/bit energy efficiency, respectively.

This paper proposes a dual-path CMOS RF-to-DC rectifier operating at 2.45-GHz with an ultra-wide high power conversion efficiency (high-PCE) input range. A new rectifier based on all NMOS rectification devices (all-NMOS) is proposed for high-power path and a modified cross-connected (CC) rectifier is designed for low-power path. The control signal for path switching is adaptively generated by auxiliary circuits without external reference or supply. The input power range with high-PCE is extended by the proposed architecture to meet the various application scenarios of energy harvesting. Implemented in a 0.18-μm standard CMOS technology, the proposed dual-path rectifier achieved a sensitivity of −20.7dBm, and it has two peak PCEs of 57% and 62% at −15dBm and 1.6 dBm, respectively. Furthermore, the PCE of the proposed dual-path rectifier can be maintained above 20% with a 27 dB input range from −22 to 5 dBm when operating at 2.45-GHz with a 50-k$\Omega$ load.

This paper presents two high-efficiency charge pumps (CPs) by utilizing the gate voltage boosting technique (GVBT). Unlike traditional bulk-CMOS and all-NMOS CPs, an input bias voltage is independently applied to the gate terminal, and it improves the current driving capability without the need of large pumping capacitors or high-frequency clocks. Meanwhile, the GVBT decouples the state of transistors from the clocks connected to the pumping capacitor, and it can eliminate the reversion loss in both main and auxiliary circuits. Fabricated in a 0.18-$\mu \text{m}$standard CMOS technology, the single-stage all-NMOS CP achieved a maximum output voltage of 6.589 V and a peak power efficiency of 80.08%. We also implemented the bulk-CMOS CP with GBVT for comparison, the single-stage all-NMOS CP achieved$\sim 1.24\times $more output voltage than the bulk-CMOS CP under a load current of 1.5 mA. The voltage errors of the all-NMOS CP between the analytical and the measured results are less than 7%.

This paper presents the high-efficiency charge pumps (CPs) that eliminate the reversion loss by using gate voltage boosting technique. First, a 6-phase bulk-CMOS CP with enhanced gate voltage is designed to reduce the reversion loss. Second, an all-NMOS CP is also demonstrated to improve the current driving capability and to break the limitation of the substrate diode breakdown voltage. The chip is designed with a 0.18-μm standard CMOS technology. As a result, the single-stage bulk-CMOS CP achieves a maximum output voltage and peak power efficiency of 6.595V and 84.2%, respectively. Moreover, the all-NMOS CP achieves ~1.2× more output voltage than the bulk-CMOS CP at 1.5mA load current.