This paper presents a 3-Level Buck Converter (3LBC) with a Fast-Flying Capacitor Charging (FFCC) technique. Unlike previous Flying Capacitor voltage (VCF) calibration methods, FFCC allows VCF to track input voltage (VIN) changes even without switching events. This continuous calibration keeps VCF close to VIN/2 and eliminates over-voltage stress during sudden VIN shifts. Additionally, FFCC enables faster calibration compared to previous methods, which were limited by the loop bandwidth due to stability concerns. FFCC, using only a comparator, achieves higher speed without stability issues. Experimental results show that with FFCC enabled, VCF stabilizes within 10µsec when VIN changes from 2.8V to 5V, compared to 3msec without FFCC. The steady-state VCF deviation remains within 1.7% of VIN/2, demonstrating FFCC's effectiveness under both transient and steady-state conditions. The proposed 3LBC achieves over 85% efficiency across a 1mA to 500mA load range, with a peak efficiency of 94.8%. The chip, fabricated in a 180nm CMOS process, occupies an area of 2.7mm x 1.7mm.

This paper proposes a ring amplifier with a self-stabilization technique (SST) against PVT variation. It can significantly alleviate the risk of the instability issue, which is particularly problematic in the front-end design. This technique automatically adjusts the dead-zone voltage (${V}_{DZ}$) according to the output voltage ringing magnitude directly. With the technique, the ring amplifier can find a suitable dead-zone voltage with minimal accuracy degradation even in a wide PVT range without adding a complex control circuit or algorithm. This technique is applied on a ring amplifier with 10-bit SAR (Successive-Approximation) ADC, and both are implemented in the 40-nm CMOS process. According to the measurement results, 51.43 dB SNDR, 60.24 dB SFDR, and 8.25-bit at 500ksps are achieved while consuming 36$\mu$W.

A switched-capacitor (SC) step-down DC-DC converter reconfiguring its open-loop topology based on the input voltage to resolve the efficiency issue of single topology is presented in this paper. An adaptive switch modulation (ASM) technique, modulating switch width of the power stage, and a frequency scaling (FS) technique, scaling the sampling rate of the PFM controller, are also proposed to reduce the quiescent current of the converter for light-load efficiency. The prototype converter in 0.25μm CMOS process with integrated flying capacitors generates a fixed regulated output voltage of 1.8V from an input voltage ranging from 3V to 4.2V. Experimental results show that the gate driving loss and the PFM controller power are decreased by more than 70% with the ASM and FS techniques. The light-load efficiencies are enhanced by 7% and 10% when the input voltage is 3V and 4V, respectively. The transient response time is about 500ns after a step current from 50μA to 10mA. Its power efficiency is high than 70% over a wide load current range with a peak value of 83%.

A 6b 1GS/s SAR ADC using 2b/cycle algorithm is presented. It cuts 50% of the capacitor arrays in conventional 2b/cycle architecture, which results in small input capacitance and low power consumption. A foreground offset calibration by adjusting MOSFET body capacitance and a common-mode noise reduction circuit are also proposed. The prototype ADC in 40-nm CMOS exhibits a peak SNDR of 34 dB at the conversion rate of 1GS/s with low frequency input and consumes 4.5mW at 1.1 V supply. It achieves a peak FoMS and FoMW of 144.5dB and 110fJ/conversion-step respectively. The core circuit occupies an area of 0.016 mm2.

This paper presents a 0.25μm HV-CMOS implementation of a Synchronous Inversion and Charge Extraction (SICE) interface circuit for piezoelectric energy harvesting. The bias-flip interfacing circuits which perform voltage inversion on the extremes of the voltage waveform have been proved effectively boosting the output power of piezoelectric energy harvesting. The proposed SICE interfacing circuit inverts the piezoelectric voltage on each extremum (bias flip action) for a given number of extremum occurrences, and then extracts the total electrostatic through the Synchronous Electric Charge Extraction (SECE) circuit. Thus, the SICE circuit is a combination of Synchronous Switch Harvesting on Inductor (SSHI) and the SECE circuits. It can achieve high power gain and be independent of loading impedance. The SICE interfacing circuit in TSMC 0.25μm HV-CMOS has been executed and taped-out. The post layout simulation results, including power consumption, circuit efficiency, and power gain will be presented in this paper.

A control method of reducing transient-glitch voltage in variable frequency (VF) DC-DC converters is proposed in this paper. By modulating the period between two hopping frequencies to a calculated time length, the proposed control method keeps the average of the inductor current undisturbed and leads to less transient effects. Simulation results show the improvements on the transient-glitch voltage, the transient settling time, and the transient spur are about 85.3%, 46.4% and 17.6dB respectively when the switching frequency hops between 1.1MHz and 3.9MHz.

Several hundreds of MS/s to 1GS/s 8-bit low-power ADCs are demanded in various portable applications. Conventional successive-approximation register (SAR) architecture has the benefits of energy efficiency and small area but it suffers from low conversion rate. Recently, multi-bit per cycle SAR [1], multi-comparator SAR [2], pipeline-SAR, and time-interleaved SAR architectures [3] are reported to improve the conversion rate. In this work, an asynchronous two-step single-channel SAR ADC using a charge sharing technique and a self-triggered-latch (STL) technique is proposed to accelerate the conversion rate and reduce the power consumption. This ADC achieves 44.3dB SNDR and 19.1 fJ/c.-s. at 900MS/s with an active core area of 0.0049 mm2 in 40nm CMOS process.

A 2nd-order curvature-compensated CMOS bandgap reference circuit with a novel trimming technique is described. The 2nd-order curvature compensation is implemented by using a temperature-dependent resistor ratio generated by a poly resistor and a diffusion resistor. A trimming technique with digital switches is utilized to increase or decrease resistance bi-directionally and therefore to minimize the variance of resistance. The proposed voltage reference operates down to a 1.5 V supply and consumes a maximum supply current of 55 /spl mu/A. The experimental prototype circuit in a standard 0.35-/spl mu/m CMOS process achieves a temperature coefficient of 10 ppm//spl deg/C and occupies an area of 0.71 mm/sup 2/.