Good FPGA placement is crucial to obtain the best Quality of Results (QoR) from FPGA hardware. Although many published global placement techniques place objects in a continuous ASIC-like environment, FPGAs are discrete in nature, and a continuous algorithm cannot always achieve superior QoR by itself. Therefore, discrete FPGA-specific detail placement algorithms are used to improve the global placement results. Unfortunately, most of these detail placement algorithms do not have a global view. This paper presents a discrete "middle" placer that fills the gap between the two placement steps. It works like simulated annealing, but leverages various acceleration techniques. It does not pay the runtime penalty typical of simulated annealing solutions. Experiments show that with this placer, final QoR is significantly better than with the global-detail placer approach.

A CAD tool, LILA, that generates layouts of both one-dimensional and two-dimensional iterative logic arrays, described in VHDL or schematic structures, is presented. Such a tool is very important because in current industry, the generation of high density iterative logic arrays (such as data paths in microprocessors) is still mainly performed manually, and is a major bottleneck of the design. In LILA, interconnections between modules (i.e., cells) of the array do not need to be between adjacent modules and functions of modules of the array do not need to be identical. Regularity in module functions and interconnections between modules are automatically extracted by the tool. Based on interconnection wire length between modules, layouts of modules and interconnections are optimized in a single step. The signals in each array module are generated in such a way that signals in adjacent modules are perfectly aligned and connected by module abutments. As no global routing or channel routing between modules are necessary, the total layout area and propagation delay between modules are minimal. The proposed system is especially useful for data path modules, bit-level systolic arrays, storage devices, and many other regular structures, and has been actually implemented in a design environment. Extensive experiments have shown that the system has a very good performance and produces layouts of very high density. The tool takes about 1.6 CPU seconds to generate an eight-by-eight array divider on a SUN SPARCstation II.>

An efficient algorithm for searching for functional cells based on Boolean matching in a large library is presented. Redundant variables and permutation of inputs are considered in this algorithm. The algorithm does a search in constant time, independent of the size of the library.>