Novel approaches for the development of integrated molecular analysis tools have been tested. A label-free method for molecular detection and characterization based on UV absorbance has been applied and two technologies of silicon photodetectors arrays have been selected to fulfil the requirements of the different applications

The paper describes the design of a smart sensor for label-free detection of DNA hybridization. The sensor is based on a direct electrical transduction principle: it measures impedance variation at the interface between a bio-functionalized electrode and a solution containing the analyte. The smart sensor includes a complete signal conditioning and processing subsystem based on an embedded /spl mu/-controller. We outline the sensor architecture, and we describe in detail board-level integration as well as hardware and software implementation and design choices. The accuracy of our embedded solution has been evaluated by comparing it with a high-cost laboratory setup. Moreover, we provide measurements of real sensing structures which demonstrate the functionality of our system in the field.

This paper presents a synthetic overview of multilevel (ML) flash memory program methods. The problem of increasing program time with the number of bits stored in each cell is discussed and methods based on both channel hot electrons (CHE) and Fowler-Nordheim tunneling (FNT) are discussed. In the case of CHE, the use of an increasing voltage rather than a constant one on the control gate (CG) leads to narrower threshold voltage distributions and smaller current absorption, with positive effects on the degree of parallelism and program throughput. As for FNT, much faster programming than that commonly used today can be done using high CG voltages without producing intolerable degradation of cell reliability.

When thinking of semiconductor memories, it comes naturally to associate stored bits and memory cells with a one-to-one relationship. That, however, is not really a must nor necessarily the most convenient solution for data storage, since using analog signals and digital-to-analog (D/A) as well as analog-to digital (A/D) conversions a large number of bits could be memorized in a single cell, although, of course, the use of analog signals presents all drawbacks of signal-to-noise ratio that are so well known in electronics. In fact, the real question in this sense concerns the number of bits used for the A/D and D/A conversions, since the conventional (fully) digital case can be seen as the simplest realization of a general approach tending to infinitely precise analog storage (i.e. an infinite number of stored bits per cell) at the other extreme. Naturally, in the real world the conflicting aspects of density (measured in bits per cell) and noise immunity (in a general sense) should be traded off one against the other looking for optimum use of silicon area, of course depending on technology, architectures, circuits and reliability. From this point of view it is obvious that the fully digital approach based on the one-bit one-cell concept does not represent necessarily the best solution. Recently, this general question has assumed real and practical significance for nonvolatile memories, since devices storing two bits per cell are now being introduced on the market. At the same time, in a number of research labs a significant effort is currently being dedicated to the study of the limits and practical convenience of storage density considering the current state of the art in technology and circuit designs. This problem, however, presents a number of interacting aspects concerning cell concept, programming and reading schemes, and architectures and reliability that are of interest well beyond the field of nonvolatile memories, because they are ultimately dealing with the basic question of analog versus digital signals. In this contrast, the present paper considers the question of multilevel nonvolatile memories in all its interacting aspects, analyzing both the current state of the art and the future possibilities.

An improved, more complete strategy for latch-up testing of CMOS ICs is proposed in order to take into account important effects that have been neglected by standard procedures, but which are shown to reduce considerably the circuit resistance to latch-up. These phenomena include interactions among carriers injected by different p-n-p-n structures, voltage drops on power supply and ground lines caused by output pin load currents, and effects of power supply voltage and chip heating. All experiments with regard to this work have been performed by means of automatic test equipment, which provides the possibility of completely controlling the circuit state and operating conditions during testing.>

The authors present a testing method for monitoring E/sup 2/PROM (electrically erasable programmable ROM) cell aging. The technique is not based on any particular assumption about cell technology: hence it can be used to characterize wearout dynamics in all cases in which charge trapped in tunnel oxide is the main failure mechanism. The method is validated by means of a wide set of measurements performed with automatic test equipment. The characterization can be directed to single cells, thus making it possible to study the main layout dependences of aging phenomena. Possible criticalities of the virgin devices (with respect to supply voltage temperature, etc.) can be determined. A procedure has been developed to extrapolate data obtained with a few programming cycles in order to obtain first-order estimates of the actual device endurance.>