Demo Data from EDBT 2026 / reviewers in the wild / expert
Hermann Meuth
dblp:76/2282
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Human-computer interaction and ubiquitous computing · 1Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 56% Integrated circuit design · 36% Energy-efficient computing · 8% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
design methodology |
0.0 | 1 | 2001 | VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers · DAC 2001 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 2001 | VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers · DAC 2001 |
Electronic design automation
logic synthesis |
0.0 | 1 | 2001 | VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers · DAC 2001 |
Integrated circuit design
low-power circuit design |
0.0 | 1 | 2001 | VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers · DAC 2001 |
Energy-efficient computing › low-power design
power and area optimization |
0.0 | 1 | 2001 | VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers · DAC 2001 |
Methods — techniques the papers use, named apart from their topics
lookup table interpolation · 0.0VHDL modeling · 0.0CORDIC · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | Designing a blended-learning Bachelor's degree in electrical engineering for non-traditional studentsabstractA blended-learning Bachelor's degree in electrical engineering is designed within the program “Upward mobility through academic training”. A questionnaire concerning learning intentions and needs returned by 144 potential non-traditional students was evaluated in the conception phase. The consequences for the design of the program are discussed. Cornelia Böhmer, Hermann Meuth, Nina Roznawski, Eva Maria Beck-Meuth |
EDUCON | 2 |
| 2004 | FPGA-Efficient Hybrid LUT/CORDIC Architecture
Ireneusz Janiszewski, Hermann Meuth, Bernhard Hoppe |
FPL | 2 |
| 2001 | VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency SynthesizersabstractDesign methodologies for high performance Direct Digital Fre-quen--cy Synthesizers (DDFS) are described. Traditional look-up tab-les (LUT) for sine and co-sine are merged with CORDIC-inter-po---la--tion into a hybrid architecture. This implements DDFS-sys-tems with high resolution without being specific to a particular tar-get technology. Amplitude constants were obtained from ma-the-matical trigonometric functions of the IEEE math_real pack-age. These constants were then written via simulation of a VHDL model into a fully synthesizable package. Systematic and detailed studies varying the synthesizers inherent parameters lead to a design optimum of the LUT/CORDIC-ra-tio, which mini-mizes power and silicon area for a given clock frequency. Ireneusz Janiszewski, Bernhard Hoppe, Hermann Meuth |
DAC | 3 |