This panel discusses the following topics. With the ongoing trend towards more and more digitization in applications ranging from multimedia to telecommunications, there is a big debate about whether there will remain a need for analog circuits in scaled technologies. Analog circuits do not seem to take advantage of nanometer CMOS; rather they suffer from it. So if the question is asked "Will analog scale?", you get conflicting opinions. One camp argues for an almost-all-digital future: analog/RF content should be limited, because it's difficult, expensive, risky, and can be done with DSP. The opposing camp counters that some critical circuits simply do not want (or need) to scale, and analog is only "risky" when you let digital designers do it. So, what is the future role of analog circuits in scaled CMOS, and can analog EDA tools help in this .

No abstract available.

One of the most important factors in achieving an accurate and efficient device simulation today is a good grid. However, an effective grid error indicator for the device simulation has been lacking; thus, it is very difficult to know how accurate the simulation results are. Previous papers have suggested that the local truncation error (LTE) is not a good indicator for grid discretization error. In this paper we show that the dominant factor in the LTE derivation has been ignored. With the correct formulation it is shown that LTE is a major source of the solution error. Since LTE is easy to calculate, our methodology provides up to orders of magnitudes savings in CPU time compared to other algorithms. This adaptive regridding on LTE provides overall simulation speedups of 10X for medium-sized examples. With little overhead, the LTE is extended to be an effective error indicator for device terminal characteristics, such as drive current and threshold voltage, which can only be obtained previously with large effort.

Selected integrated circuit (IC) reliability issues are discussed within the context of the design-in reliability concept. The electrical reliability issues discussed are latchup, electrostatic discharge, hot carrier effects, thin dielectric breakdown, and electromigration. Examples of the environmental reliability issues discussed are alpha -particle induced soft errors, thermal stress, mechanical stress, and corrosion.>

Algorithms for transient mixed-level circuit and device simulation using a full two-carrier three-dimensional (3-D) device simulator SIERRA and the circuit simulator SPICE3 are presented. Circuit and device simulator coupling algorithms that are suited for two-dimensional mixed-level circuit and device simulation using direct solvers cannot be successfully employed when iterative solution techniques are used in 3-D device simulation. New algorithms to couple the circuit and 3-D device simulator have been developed and evaluated. The importance of 3-D mixed-level circuit and device simulation is demonstrated by applying it to single-event upset in CMOS SRAM cells.>

The authors describe algorithms for transient mixed-level circuit and device simulation using a two-carrier three-dimensional device simulator SIERRA and the circuit simulator SPICE3. It is pointed out that algorithms well suited to 2D mixed-level circuit and device simulation cannot be successfully used. The memory and CPU time requirements in 3D device simulation necessitate it the use of iterative solution techniques at the device level, which impose an additional constraint in developing efficient algorithms. Two node tearing schemes are shown to be the most promising schemes for coupling the circuit and device simulators. An application of 3D mixed-level simulation to the study of single-event upset of SRAM cells is presented.>

The authors present a general purpose, parallel matrix solver based on the conjugate gradient squared (CGS) method which features a novel preconditioning scheme commensurate with massive parallel computing. The solver algorithm has been successfully used for solving linear systems of equations arising from circuit and device simulations with MOS and bipolar junction transistor (BJT) circuits, both digital and analog, as well as high-level injection conditions in devices. The performance of the algorithm can be further improved by a matrix partitioning scheme.>

Two techniques for general circuit simulation, an intelligent, partial Gauss-Seidel scheme (PGS) and a preconditioned conjugate-gradient scheme (PLUCGS), are described. Both techniques are robust and accurate for bipolar and MOS analog and digital circuits. PGS is a novel combination of direct solution, using LU factorization, and iterative solution, using Gauss-Seidel relaxation. The method converges faster and more reliably than Gauss-Seidel, while taking a comparable amount of execution time per iteration. Solution speeds up to 6 times faster than direct methods have been demonstrated and higher grains are anticipated for larger circuits. The second method, PLUCGS, uses a partial LU factorization as a preconditioner; a vectorized implementation on a CONVEX C-240 computer is 5-7 times faster than the direct solution method with only one-fourth the memory requirements.>

SIERRA is a 3-D general-purpose semiconductor-device simulation program which serves as a foundation for investigating integrated-circuit (IC) device and reliability issues. This program solves the Poisson and continuity equations in silicon under DC, transient, and small-signal conditions. Executing on a vector/parallel minisupercomputer, SIERRA utilizes a matrix solver which uses an incomplete LU (ILU) preconditioned conjugate gradient square (CGS, BCG) method. The ILU-CGS method provides a good compromise between memory size and convergence rate. The authors have observed a 5* to 7* speedup over standard direct methods in simulations of transient problems containing highly coupled Poisson and continuity equations such as those found in reliability-oriented simulations. The application of SIERRA to parasitic CMOS latchup and DRAM (dynamic random-access memory) single-event-upset studies is described.>

An analytical predictor/CAD model for a short-channel buried-channel MOSFET is reported. The proposed model can be used to predict the anomalous threshold voltage shift associated with the short-channel buried-channel MOSFET. The characteristic is shown to be caused by the shifting of the operational mode from the surface to the buried channel. Current equations which are applicable to the short-channel buried-channel device are derived. For the purpose of circuit simulations, a computationally efficient CAD current model is also developed. The current characteristics calculated from the model equation are found to be in good agreement with experimental results. By using the CAD current equations, a charge model for the intrinsic buried-channel device is formulated. The charge model equations can be used to model the intrinsic capacitances for SPICE simulations.