This paper presents a high-precision, low-loss, fully on-chip current detection scheme for a monolithic integrated GaN half-bridge in high-voltage isolated converters. The proposed design integrates power switches, gate drivers, an on-chip current sensor and a relative-negative voltage supply using a GaN-on-SOI process, addressing challenges posed by parasitic inductance and signal transmission delays. To enhance detection accuracy and minimize power loss, a sense-HEMT scheme with an amplifier clamping loop featuring auto-zeroing is utilized. The simulation results show that the current detection accuracy of the proposed design surpasses 96%, and is sucessfully demostrated in an active clamp flyback converter. Additionally, a multi-stage self-cycling and bootstrap driver is proposed, characterized by driving delays of ton=6.5 ns and toff=6.3 ns, and proving a rail-to-rail driving voltage.

Photoacoustic (PA) imaging technology integrates the deep penetration depth of ultrasound imaging with the high resolution of optical imaging, demonstrating significant potential in biomedical applications. Many preclinical studies and clinical applications urgently require a portable, high-quality, low-cost, and fast imaging system. Thus, translating advanced image reconstruction algorithms into hardware implementations is highly desired. However, existing iterative PA image reconstructions, although exhibit higher accuracy than the delay-and-sum algorithm, suffer from high computational cost. In this paper, we introduce a novel model-based hardware architecture for palm-size PA tomography (palm-PAT), aiming at enhancing both the speed and performance of image reconstruction at a much lower system cost. To achieve this, we propose an innovative data reuse method that significantly reduces the consumption of hardware storage resources, achieving a reduction of approximately 75% in hardware storage requirements. We conducted experiments utilizing the FPGA implementation of the algorithm, using phantom, human finger data in vivo and ex vivo breast tumor data to verify the feasibility of the proposed method. The results demonstrate that our proposed architecture can substantially reduce system cost while maintaining high imaging performance. The novel hardware architecture design of the model-based algorithm achieves a speedup of up to approximately 270 times compared to the CPU, while the corresponding energy efficiency ratio is improved by more than 2700 times.

This paper presents an auto-polarity thermo-electric energy harvesting circuit based on the reconfigurable thermoelectric generator (TEG) array. The auto-polarity function is achieved by simply altering the operating mode of the inverse current detector without adding extra power overhead and hardware cost. In addition, the proposed circuit consists of the TEG array and switches, removing the need for bulky inductor-based or switched-capacitor DC-DC converters. Hill-climbing algorithm is used for maximum power point tracking (MPPT). The operating frequency of the system is 0.2 Hz with overall dynamic power consumption of only 1.2mW. Over a wide range of temperature gradients, the static power is less than$0.1\mu \mathrm{W}$with a peak efficiency of 99.6%.

This paper presents a fully-integrated half-bridge GaN driver for bidirectional power transfer. Three-level/bipolar gate driver is introduced for the power switches to improve reliability at high dv/dt. On-chip bootstrap circuit with charge sharing reduces chip area and protects high-side switch. The designed GaN driver is fabricated with a 0.18μm BCD process. Measurement results show that at 5MHz operating frequency, the highest input voltage reaches 40V in buck mode and the highest output voltage ups to 36V in boost mode. The peak efficiencies of the design are 93.21 % for the 20V-to-12V conversion and 91.17% for the 12V -to-18V conversion. The design delivers a maximum power of 21.15W in buck mode.

This paper presents a comparative study of high-frequency chopping and low-frequency chopping. Several key parameters of a chopper-stabilized amplifier are analyzed in detail. To verify the effect of chopping frequency, a general-purpose chopper-stabilized amplifier is designed and implemented with a$0.18-\mu \mathrm{m}$CMOS process. Simulations show that the input biasing current, thermal noise level, and input offset voltage are all related to the chopping frequency.

This paper presents a gate driver for a GaN-based half-bridge structure operating in a buck converter with input voltage >40 V or a boost converter with output voltage >30 V. Two 500 pF on-chip capacitors are utilized to construct three-level gate drivers, providing a near-$V_{{\text {DD}}}$negative voltage for gate of the rectifier switch to eliminate the induced pulse on the gate from the highdv/dtslew rate of$V_{\text {X}}$when the main switch is turned on. The dead time controller tunes the delay of the gate signal of the rectifier switch by sensing the slope of$V_{\text {X}}$, thus the near-optimal zero-voltage switching can be achieved with deviation$\mu \text{m}$BCD process. The efficiencies can be improved by 8.33% and 6.87% at light load in a buck and a boost converter due to the dead-time control. The peak efficiencies of 20 V–12 V and 12 V–18 V conversions are 86.37% and 84.39%, respectively.

A 5.5W mains-powered converter-free LED driver for general lighting application is presented in this summary for the university design contest. The driver is superior to its switching converter based counterparts as it does not require any bulky and expense magnetics or electrolytic capacitors. In addition, the driver is able to significantly reduce the flicker at light output with a quasi-constant power control scheme. The measurement results show that the prototype driver achieves 88.2% efficiency and 0.92 power factor with only 18% flicker at 110VAC 60Hz input.

A more accurate steady state analysis of the zero-voltage switching quasi-resonant (ZVSQR) converter is conducted in this paper. The conversion ratio equation and the conditions to achieve zero-voltage switching (ZVS) are derived. According to the analysis, a ZVSQR converter can be designed to operate within a wider input voltage range. A ZVSQR inverted buck converter is simulated as an example to verify the analytical results.