In this paper, a high performance lossless color image compression and decompression architecture to reduce both memory requirement and bandwidth is proposed. The proposed architecture consists of differential-differential pulse coded modulation (DDPCM) and Golomb-Rice coding. The original image frame is organized as m by n sub-window arrays, to which DDPCM is applied to produce one seed and m × n - 1 pieces of differential data. Then the differential data are encoded using the Golomb-Rice algorithm to produce losslessly compressed data. According to the experimental results on benchmark images, the proposed architecture can guarantee high enough compression rate and throughput to perform real-time lossless CODEC operations with a reasonable hardware area.

For the low-cost hardware-based intrusion detection systems, this paper proposes a memory-efficient parallel string matching scheme. In order to reduce the number of state transitions, the finite state machine tiles in a string matcher adopt bit-level input symbols. Long target patterns are divided into subpatterns with a fixed length; deterministic finite automata are built with the subpatterns. Using the pattern dividing, the variety of target pattern lengths can be mitigated, so that memory usage in homogeneous string matchers can be efficient. In order to identify each original long pattern being divided, a two-stage sequential matching scheme is proposed for the successive matches with subpatterns. Experimental results show that total memory requirements decrease on average by 47.8 percent and 62.8 percent for Snort and ClamAV rule sets, in comparison with several existing bit-split string matching methods.

This paper proposes an algorithm that provides both dynamic voltage scaling and power shutdown to minimize the total energy consumption of an application executed on an on-chip multiprocessor. The proposed algorithm provides an extended schedule and stretch method, where task computations are iteratively stretched within the slack of a time-constrained dependent task set. In addition, the break-even threshold interval for amortizing the shutdown overhead is considered. By evaluating each set of stretched task computations, an energy-efficient set is obtained. The proposed dynamic voltage scaling efficiency metric is the ratio of the reduced energy to the increased cycle time when the supply voltage is scaled, which can be used to determine the task computation cycle to be stretched. Experimental results show that the proposed algorithm outperforms the traditional schedule and stretch method in the various evaluations of target real applications.

A new methodology to increase the encoding efficiency of test compression based on linear feedback shift registers (LFSRs) is proposed. The proposed method combines LFSR reseeding and bit fixing. Deterministic test patterns tend to have a biased probability of the logic value 1 or 0 at each primary input. If such biased inputs are fixed to the logic value 1 or 0 with some combinational logic, then the amount of data to be encoded by the LFSR will be considerably reduced. Additionally, in order to reduce the encoded data volume much further, a variable degree of the LFSR polynomial is employed. In the variable-degree LFSR scheme, a test cube with less specified bits is encoded with an LFSR polynomial of lower degree, while a test cube with more specified bits is encoded with an LFSR polynomial of higher degree. Experimental results for the larger ISCAS 89 benchmark circuits show that the proposed scheme can increase the encoding efficiency with little hardware overhead compared to previous schemes.

A new test-decompression methodology using a variable-rank multiple-polynomial linear feedback shift register (MP-LFSR) is proposed. In the proposed reseeding scheme, a test cube with a large number of specified bits is encoded with a high-rank polynomial, while a test cube with a small number of specified bits is encoded with a low-rank polynomial. Therefore, according to the number of specified bits in each test cube, the size of the encoded data can be optimally reduced. A variable-rank MP-LFSR can be implemented with a slight modification of a conventional MP-LFSR. The experimental results on the largest ISCAS'89 benchmark circuits show that the proposed methodology can provide much better encoding efficiency than the previous methods with adequate hardware overhead.

We present a new transparent SRAM test algorithm, which uses dynamic power supply current. The proposed test scheme employs the dynamic power supply current instead of making signatures, so that it does not need the additional steps and additional hardware to generate signatures. This paper describes how to convert a traditional March algorithm to a transparent one. The transformed algorithm is much simpler and the test time can be reduced very much. In addition, it can detect some additional faults that the original algorithm cannot detect.

The number of weighted random patterns depends on the number of deterministic test patterns with a low sampling probability. The weight set that is extracted from the deterministic pattern set with high sampling probability reduces the number of test patterns. In this paper we present a new deterministic pattern selection algorithm which generates high performance weight sets by removing deterministic patterns with low sampling frequencies. Simulation results using ISCAS 85 benchmark circuits prove the effectiveness of the new weight set generation algorithm.

The number of weighted random patterns depends on the sampling probability of the corresponding deterministic test pattern. Therefore if the weight set is extracted from the deterministic pattern set with high sampling probabilities, the test length can be shortened. In this paper we present a new multiple weight set generation algorithm that generates high performance weight sets by removing deterministic patterns with low sampling probabilities. In addition, the weight set that makes the variance of sampling probabilities for deterministic test patterns small, reduces the number of the deterministic test patterns with low sampling probability. Henceforth we present a new weight set calculation algorithm that uses the optimal candidate list and reduces the variance of the sampling probability. The results on ISCAS 85 and ISCAS 89 benchmark circuits prove the effectiveness of the new weight set calculation algorithm.