This paper presents a current-mode DC-DC buck converter with a wide input/output dynamic range, enabling fast, accurate, and seamless peak-valley transition to support dynamic voltage scaling (DVS) in application processors (APs). The wide input/output dynamic range is achieved through the proposed reconfigurable current-mode controller synchronised with an external frequency. Furthermore, the proposed parameter- and parasitic-sensed critical duty detector (PPSCDD) facilitates accurate and seamless peak-valley transitions at the actual critical duty, which is detected in a closed-loop operation by sensing all parameters and parasitic non-idealities through dedicated filter networks. The converter is implemented in standard 180 nm CMOS with an active area of 0.483 mm2, operating over an input range of 2.0-3.3 V, supporting an output range of 0.5-2.5 V for$V_{IN} \geq 3$V. The converter achieves fast reference tracking (<760ns) for small reference steps of ±200mV, enabling rapid and accurate voltage scaling transitions. Even with a large reference step, the seamless peak-valley transition ensures accurate output tracking. At a load slew rate of 1A/ns (0.1-1 A step), the converter achieves 25 mV undershoot and 20mV overshoot, with settling times of 220ns and 300ns, respectively.

The double-layer cell capacitance (Cdl) in electrochemical sensing varies significantly, which is determined by the amount of redox reaction and the structure of an electrochemical cell. The traditional voltage-driven potentiostat architecture is stable only over a limited range of Cdl, thus restricting its utility for wide-proliferated electrochemical cells. This paper proposes a current-driven potentiostat architecture that enhances the stability of the overall system across more than ten decades of Cdl. The proposed architecture also works under a unipolar power supply, eliminating the need for bipolar supply voltages as required in the conventional voltage-driven potentiostat. The analog front end (AFE) of the proposed architecture has been developed on a printed circuit board (PCB), and its efficacy has been experimentally validated.

In this paper, a pattern generator architecture is presented to generate the staircase and square waves for electro-chemical sensing. The proposed system consists of a finite-state machine (FSM) stage to produce a specific counting sequence, a selector block and a pattern generation block to produce such patterns from an external reference clock. The system produces both the staircase and square patterns needed for performing voltammetry in the electrochemical sensing. The proposed pattern generator is designed using a standard CMOS 180 nm technology. The staircase pattern shows a linear behaviour with an uniform step size of ∼76.9 mV varying from 1 V to 2 V. The generated square wave has a a peak-to-peak voltage of ∼153.8 mV and its local average coincides with the same of the staircase pattern in each step enabling an accurate matching of these two patterns. The system consumes an average power of 916 µW at a supply voltage of 2.7 V.

This paper presents a single-inductor, multiple-output (SIMO) DC-DC converter suitable for the micro-battery-powered IoT (Internet-of-Things) applications operating with a very low activity factor. Targeting an average output power of few$\mu $W with a peak output power requirement of a few mW in each output channel, the proposed converter transfers constant-charge to its outputs in a complete switching cycle. Multiple IoT nodes are serviced in a time-division multiplexing under discontinuous conduction mode (DCM) of operation for minimizing the cross-regulation issue. An internal priority sequencing logic ensures reliable power-up sequencing during startup. Additionally, the proposed SIMO converter offers an inherent soft-start mechanism, effectively mitigating current-stress on power MOSFETs. Also, the features of priority-based servicing under dynamic conditions, resolve a conflict when catering to multiple outputs at the same instant. The design is highly scalable towards meeting the increased load demand. Implemented in a standard 180 nm CMOS technology, the proposed converter generates three outputs (0.9 V, 1.2 V and 1.5 V) with a maximum load current of 5 mA simultaneously in each of the output channels. Using a single inductor of$10~\mu \text{H}$and an output capacitor of$10~\mu \text{F}$in each of the outputs, the proposed converter shows an output ripple < 22 mV with a peak power efficiency of 91.73%.

This paper introduces a time-to-voltage converter-based maximum power point tracking (TVCB-MPPT) for harvesting photovoltaic energy into a super-capacitor using a single solar cell. In the proposed design, a time-to-voltage converter is used to achieve a fast and accurate tracking of the maximum power point (MPP) without using a time-averaging/time-integrating function as used in the conventional time-based MPPT design. Moreover, with the continuous monitoring of the MPP, the proposed converter responds immediately and maximizes the extracted energy under varying irradiance conditions as compared to the conventional intermittent MPPT topologies. The addition of the cold-start operation and the over-voltage protection increase the robustness and energy-autonomy of the overall system. The proposed TVCB-MPPT converter is fabricated in a 180 nm CMOS process. In the measured result, a fast online MPP tracking time of$440~\mu $s is observed with an initial tracking time of 4.8 ms. It also shows a peak tracking efficiency of 99.7% with a power conversion efficiency >87% in the entire input power range.

Single-stage regulator topologies are often preferred in embedded applications due to their low power consumption with a single-pole behavior, resulting in easy frequency compensation. Since the achievable differential gain from a single stage is low, the dc load regulation is poor over a wide dynamic range. This paper presents a single-stage, adaptively biased, low-dropout regulator to achieve a comparable dc load regulation similar to multistage topologies. This is achieved mainly by modifying the adaptive bias loop which amplifies both the common-mode and differential-mode signals. In addition, as the proposed regulator is stable for a wide range of output capacitors, including the capacitor-less (on-chip) and with-capacitor (off-chip) conditions, it is suitable for more generic applications. The proposed regulator is implemented in a standard 0.18-μm CMOS technology. The experimental results show that the regulator is capable of delivering up to 100 mA with a dc load regulation of 0.140 mV/mA and is stable with Co≤3.3 nF (capacitor-less) and Co≥1 μF (with-capacitor).