Understanding how emotional expression in language relates to brain function remains a key challenge in neuroscience. Traditional neuroimaging provides valuable insight but is costly and limited to controlled laboratory settings. Here, we present a computational framework that explores potential links between emotional content in natural language and neuro-anatomical regions associated with affective processing. This, when validated through complementary neuroimaging, may enable scalable, imaging-free investigation of emotion-brain relationships. Our approach combines text embeddings, dimensionality reduction, and clustering to identify emotional states, which are then mapped to relevant brain regions. The framework was evaluated across three applications: (i) comparing healthy and depressed individuals, (ii) analyzing a large-scale emotion dataset, and (iii) contrasting human and large language model (LLM) outputs. Emotion intensity was quantified using a lexical scoring system sensitive to keywords, syntax, and modifiers, producing computationally plausible emotion-to-region clusters with visualization mapping. Across experiments, the framework distinguished healthy from depressed participants through distinct computational activation patterns and revealed systematic differences between human and LLM-generated texts in predicted computational engagement. A key finding emerged: depressed individuals exhibited reduced emotional diversity, showing 2.2 - 2.7 times more homogeneous emotional expression than healthy controls, suggesting that emotional rigidity may serve as a computational marker of depression. These computational patterns represent testable hypotheses, requiring further validation through neuroimaging. This work establishes a scalable, cost-effective tool for advancing both clinical and computational models of emotion, and provides a neuro-inspired benchmark for assessing how closely AI-generated language mirrors human emotional expression.

Spiking Neural Networks (SNNs) offer a low-power alternative to conventional deep neural networks by leveraging their sparse, event-driven processing for both static and event-based data. While previous spiking autoencoders were energy-intensive and limited to static inputs, this work presents a novel spiking autoencoder capable of efficiently reconstructing both static and spatiotemporal data with high fidelity. To benchmark spatial pattern reconstruction, we evaluate performance on the MNIST and Fashion-MNIST datasets. Our autoencoder encodes each static input using just a single spike, reducing total energy consumption to an estimated 2.54 mJ across the entire training and testing phases. We also propose a novel decoder neuron model that enables fine-grained control over output spike timing, achieving over a 1000 × improvement in reconstruction quality compared to prior unsupervised Spike Timing Dependent Plasticity (STDP)-based methods. Additionally, we show that our model’s reconstruction performance is close to state-of-the-art autoencoders that rely on computationally intensive supervised, gradient-based convolutional networks. To validate performance on spatiotemporal data, we use the Spiking Heidelberg Digits (SHD) dataset and examine the trade-off between energy efficiency and reconstruction accuracy. Our results show that the reconstructions preserve most of the original information, while capping total energy use at 127 mJ for the full training and testing cycle. These findings lay a foundation for designing more efficient and scalable SNNs for real-world applications.

This paper presents an analysis of the application of an intentionally mismatched capacitive Digital-to-Analog Converter (CDAC) to improve the area efficiency and accuracy of successive-approximation register (SAR) analog-to-digital converters. The proposed SAR ADC architecture, the redundant capacitor-saver SAR ADC, utilizes 1-bit redundancy with intentional mismatch to estimate an additional resolution bit. This redundancy bit not only enhances noise tolerance but also achieves higher resolution through area- and energy-efficient computations, without requiring the addition of non-ideal, area-consuming, and energy-intensive capacitors to the CDAC block of the conventional SAR ADC. Simulations were conducted using Cadence TSMC 130nm CMOS technology and MATLAB software for conventional, redundant, and redundant capacitor-saver SAR ADCs, demonstrating 3 dB and 2 dB improvements in SNDR and SFDR, respectively, when using the capacitor-saver DAC architecture.

This paper proposes Matrix Sorting (MATSORT), a novel algorithm for compressing sparse matrices to enable efficient execution of sparse Multiply-Accumulate (MAC) operations in parallel computing architectures for Deep Neural Networks (DNNs). Pruning in DNNs often results in weight matrices with a large proportion of zero weights, leading to significant resource and time wastage when processed by parallel computing architecture. MATSORT outperforms state-of-the-art (SoTA) techniques in both compression speed and compression rate—two key factors for efficient sparse MAC operations. The algorithm employs an approximate sorting method and a novel merging strategy, reducing the sorting time complexity while resolving long-standing element conflict issues. These optimizations achieve nearly 100% compression rates across all tested matrices, substantially enhancing power and resource efficiency. Evaluation results show that MATSORT delivers a maximum speedup of 441× for a 1280 × 1280 matrix and a minimum speedup of 1.63× for a 110 × 128 matrix, outperforming existing methods.

Spiking Auto-Encoders (SAEs) have the potential to greatly outperform deep learning auto-encoders in power efficiency, yet their performance remains a challenge. This work enhances both power efficiency and accuracy by reducing spike counts and introducing key innovations. We propose a novel decoder neuron model that enables precise spike timing and implement a weight-dependent Spike-Timing-Dependent Plasticity (STDP) mechanism in the encoder for better feature learning. Our architecture encodes static MNIST images using only a single spike and reconstructs spatio-temporal data from the Spiking Heidelberg Digits (SHD) dataset, optimizing the spike count for reconstruction. This substantial reduction in spike usage translates to a marked improvement in power efficiency. In addition, the average Mean Square Error (MSE) for the MNIST images was found to be 0.039, representing a 99.93% reduction from previous results. These improvements advance neuromorphic systems toward more practical, efficient applications.

Shadows significantly hinder computer vision tasks in outdoor environments, particularly in field robotics, where varying lighting conditions complicate object detection and localization. We present FieldNet, a novel deep learning framework for real-time shadow removal, optimized for resource-constrained hardware. FieldNet introduces a probabilistic enhancement module and a novel loss function to address challenges of inconsistent shadow boundary supervision and artefact generation, achieving enhanced accuracy and simplicity without requiring shadow masks during inference. Trained on a dataset of 10,000 natural images augmented with synthetic shadows, FieldNet outperforms state-of-the-art methods on benchmark datasets (ISTD, ISTD+, SRD), with up to 9x speed improvements (66 FPS on Nvidia 2080Ti) and superior shadow removal quality (PSNR: 38.67, SSIM: 0.991). Real-world case studies in precision agriculture robotics demonstrate the practical impact of FieldNet in enhancing weed detection accuracy. These advancements establish FieldNet as a robust, efficient solution for real-time vision tasks in field robotics and beyond. • FieldNet: Novel deep learning for shadow removal in robotics. • Real-time: 66 fps on Nvidia 2080Ti for outdoor applications. • New loss boosts shadow boundary accuracy with context. • Dataset: 10,000 images with synthetic shadows for robustness. • Outperforms state-of-the-art on three benchmark datasets.

One of the main challenges in deep learning-based underwater image enhancement is the limited availability of high-quality training data. Underwater images are often difficult to capture and typically suffer from distortion, colour loss, and reduced contrast, complicating the training of supervised deep learning models on large and diverse datasets. This limitation can adversely affect the performance of the model. In this paper, we propose an alternative approach to supervised underwater image enhancement. Specifically, we introduce a novel framework called Uncertainty Distribution Network (UDnet), which adapts to uncertainty distribution during its unsupervised reference map (label) generation to produce enhanced output images. UDnet enhances underwater images by adjusting contrast, saturation, and gamma correction. It incorporates a statistically guided multicolour space stretch module (SGMCSS) to generate a reference map, which is utilized by a U-Net-like conditional variational autoencoder module (cVAE) for feature extraction. These features are then processed by a Probabilistic Adaptive Instance Normalization (PAdaIN) block that encodes the feature uncertainties for the final image enhancement. The SGMCSS module ensures visual consistency with the input image and eliminates the need for manual human annotation. Consequently, UDnet can learn effectively with limited data and achieve state-of-the-art results. We evaluated UDnet on eight publicly available datasets, and the results demonstrate that it achieves competitive performance compared to other state-of-the-art methods in both quantitative and qualitative metrics. Our code is publicly available at https://github.com/alzayats/UDnet.

Achieving fully autonomous driving with enhanced safety and efficiency relies on vehicle-to-everything (V2X) cooperative perception (CP), which enables vehicles to share perception data, thereby enhancing situational awareness and overcoming the limitations of the sensing ability of individual vehicles. V2X CP plays a crucial role in extending the perception range, increasing detection accuracy, and supporting more robust decision-making and control in complex environments. This article provides a comprehensive survey of recent developments in V2X CP, introducing mathematical models that characterize the perception process under different collaboration strategies. Key techniques for enabling reliable perception sharing, such as agent selection, data alignment, and feature fusion, are examined in detail. In addition, major challenges are discussed, including differences in agents and models, uncertainty in perception outputs, and the impact of communication constraints such as transmission delay and data loss. This article concludes by outlining promising research directions, including privacy-preserving artificial intelligence methods, collaborative intelligence, and integrated sensing frameworks to support future advancements in V2X CP.

This paper conducts a detailed analysis of the impact of channel charge injection on the capacitive digital-to-analog (DAC) block in successive-approximation register (SAR) analog-to-digital converters (ADCs). It introduces a CAD tool for distinguishing various non-idealities, quantifying channel charge injection across all possible binary output codes. It enables the implementation of more effective compensation methods rather than relying on simple dummy switches by detecting most effective switches. All simulations are conducted using Cadence TSMC 130nm CMOS technology and MATLAB software, implying on 5 to 7 dB degradation in SNDR when considering the effect of channel charge injection in 6, 9, and 12-bit typical SAR ADCs.

Transformers have emerged as the state-of-the-art architecture for natural language processing (NLP) and computer vision. However, they are inefficient in both conventional and in-memory computing architectures as doubling their sequence length quadruples their time and memory complexity due to their self-attention mechanism. Traditional methods optimize self-attention using memory-efficient algorithms or approximate methods, such as locality-sensitive hashing (LSH) attention that reduces time and memory complexity from O(L2) to O(L log L). In this work, we propose a hardware-level solution that further improves the computational efficiency of LSH attention by utilizing in-memory computing with semi-passive memristor arrays. We demonstrate that LSH can be performed with low-resolution, energy-efficient 0T1R arrays performing stochastic memristive vector-matrix multiplication (VMM). Using circuit-level simulation, we show our proposed method is feasible as a drop-in approximation in Large Language Models (LLMs) with no degradation in evaluation metrics. Our results set the foundation for future works on computing the entire transformer architecture in-memory.

Conventional surrogate Back-Propagation-Through-Time learning in Spiking Neural Networks (SNN) demands excessive energy consumption when simulating over extended time intervals. Moreover, the spike encoding process necessitates intricate hardware support, thus undermining overall efficiency. Additionally, their classification accuracies fall short in comparison to artificial neural networks due to the inherent information loss in spike translation. Therefore, there is a critical need for efficient techniques that can enhance performance without compromising accuracy. In this study, we introduce a novel learning scheme that harnesses lossless phase coding. This approach allows us to achieve minimal inference latency, requiring a maximum of at most 8 simulation steps. Furthermore, our training times exhibit significant reductions when compared to previous single-spike networks. Our experimental results demonstrate that Phase-SNN attains state-of-the-art accuracy levels, achieving 98.6% and 89.6% accuracies on the MNIST and Fashion-MNIST datasets, respectively.

In this work, we present a memristor crossbar array-based hardware architecture designed to solve a system of differential equations for the Hodgkin-Huxley neuron model. The system extends from previous works to perform more computations in-memory, reducing the load of software processing and distributing them onto memristive hardware along with cheap shift-and-add operations. We demonstrate the properties of the solutions produced by the system follow the expected behaviours of the Hodgkin-Huxley model under various external currents.

As machine learning (ML) algorithms, particularly neural networks (NN), expand in popularity and capacity, the quest for more efficient computation methods gains momentum. Memristor crossbar technology emerges as a promising alternative to traditional computing units, aiming to address traditional computing challenges. However, conventional matrix-vector multiplication (MVM) methods on these platforms are often plagued by device imperfections and drift. In this work, we introduce an innovative lightweight calculation approach leveraging bit-transformation for MVM, significantly enhancing operation precision and, consequently, the performance of ML algorithms on memristor crossbar platforms. We provide details of the core algorithm and its extensions, furnish digital validation, and simulate its efficacy using an autoencoder (AE) neural network with an extended VTEAM model. Our tests demonstrate an average reconstruction precision improvement of approximately 53.5%. This work’s applicability extends beyond NNs, offering a foundational method for conducting more precise analog MVM operations.

Auto-encoders are capable of performing input re-construction through an encoder-decoder structure. These net-works can serve many purposes such as noise removal and anomaly detection, whilst being trained without the need for labelled data. Spiking auto-encoders can utilise asynchronous spikes to potentially improve power and simplify the required hardware. In this work, we propose an efficient spiking auto-encoder with novel error-modulated STDP learning. Our auto-encoder uses the Time To First Spike (TTFS) encoding scheme and needs to update all synaptic weights only once per input. Also, it needs only an average of 8 spikes in its hidden layer for reconstruction, leading to a very sparse and hence potentially power-efficient implementation. We demonstrate decent reconstruction ability for MNIST and the challenging Caltech Face/Motorbike datasets and achieve excellent noise removal from MNIST images.

This paper presents a hybrid pipeline SAR ADC with a loop-unrolled structure to reduce the crossbar’s ADC power while maintaining high speed. The 1ststage memristive SAR ADC can fully utilize the TIA originally in the crossbar and avoid the extra MDAC in pipeline ADC. Further, memristive weight calibration and a new resistive alternated binary search are implemented on the 1ststage to maintain the TIA gain and ADC’s accuracy. Both stage’s ADC are loop-unroll to eliminate the delay brought by SAR logic for high speed. Through multiple simulations, the design is demonstrated to be robust to the frequency and mismatch variations with the highest sampling frequency reaching 300MHz and SNDR up to 65.1dB in 9MHz input. The power consumption is designed to be as low as 6.7mW, which helps the ADC to achieve a 15.2fJ/conv FoM. Not limited to the crossbar, the presented ADC also shows promising potential for applications in various fields (biomedical, IoT etc.) for general purposes.

Marine ecosystems and their fish habitats are becoming increasingly important due to their integral role in providing a valuable food source and conservation outcomes. Due to their remote and difficult to access nature, marine environments and fish habitats are often monitored using underwater cameras to record videos and images for understanding fish life and ecology, as well as for preserve the environment. There are currently many permanent underwater camera systems deployed at different places around the globe. In addition, there exists numerous studies that use temporary cameras to survey fish habitats. These cameras generate a massive volume of digital data, which cannot be efficiently analysed by current manual processing methods, which involve a human observer. Deep Learning (DL) is a cutting-edge Artificial Intelligence (AI) technology that has demonstrated unprecedented performance in analysing visual data. Despite its application to a myriad of domains, its use in underwater fish habitat monitoring remains under explored. In this paper, we provide a tutorial that covers the key concepts of DL, which help the reader grasp a high-level understanding of how DL works. The tutorial also explains a step-by-step procedure on how DL algorithms should be developed for challenging applications such as underwater fish monitoring. In addition, we provide a comprehensive survey of key deep learning techniques for fish habitat monitoring including classification, counting, localisation, and segmentation. Furthermore, we survey publicly available underwater fish datasets, and compare various DL techniques in the underwater fish monitoring domains. We also discuss some challenges and opportunities in the emerging field of deep learning for fish habitat processing. This paper is written to serve as a tutorial for marine scientists who would like to grasp a high-level understanding of DL, develop it for their applications by following our step-by-step tutorial, and see how it is evolving to facilitate their research efforts. At the same time, it is suitable for computer scientists who would like to survey state-of-the-art DL-based methodologies for fish habitat monitoring.

Abstract Tracking fish movements and sizes of fish is crucial to understanding their ecology and behaviour. Knowing where fish migrate, how they interact with their environment, and how their size affects their behaviour can help ecologists develop more effective conservation and management strategies to protect fish populations and their habitats. Deep learning is a promising tool to analyse fish ecology from underwater videos. However, training deep neural networks (DNNs) for fish tracking and segmentation requires high-quality labels, which are expensive to obtain. We propose an alternative unsupervised approach that relies on spatial and temporal variations in video data to generate noisy pseudo-ground-truth labels. We train a multi-task DNN using these pseudo-labels. Our framework consists of three stages: (1) an optical flow model generates the pseudo-labels using spatial and temporal consistency between frames, (2) a self-supervised model refines the pseudo-labels incrementally, and (3) a segmentation network uses the refined labels for training. Consequently, we perform extensive experiments to validate our method on three public underwater video datasets and demonstrate its effectiveness for video annotation and segmentation. We also evaluate its robustness to different imaging conditions and discuss its limitations.

In practical fuzzy applications, such as image processing, the utilization of precise models in hardware may not be the most efficient approach due to increased energy consumption and chip resource allocation. In a fuzzy system, an approximate implementation of min-max blocks offers an efficient solution with minimal accuracy compromise. Nevertheless, recent designs predominantly employ noncommercialized technologies for the fundamental fuzzy blocks. This article introduces a novel hardware solution for approximate fuzzy image edge detection using the well-established independent gate Fin field-effect transistor (FinFET) technology. The proposed hardware leverages two inference rules to identify edge pixels effectively. The fuzzy inference engine is implemented at the circuit level using 24 FinFETs, whereas the defuzzifier section incorporates four FinFETs with a configurable thresholding structure for optimal performance. Our circuit-level simulations reveal a remarkable 71% reduction in energy consumption compared with previous designs. The edge detection results are compared at the system level with the MATLAB Sobel edge detector. The proposed approximate hardware consistently matches the Sobel edge detection outcomes, exhibiting a 15% average improvements in data loss rate than other approximate structures. A figure of merit (FoM) is introduced to provide a comprehensive evaluation, considering both circuit and system-level metrics. The proposed FinFET-based hardware outperforms other approximate and even exact fuzzy edge detection hardware designs, boasting a 1.8 times higher FoM. This design paradigm exemplifies a promising direction toward compact and energy-efficient on-chip hardware implementations of real-world fuzzy systems.

Single-cell RNA sequencing is an emerging technique in the field of biology that departs radically from the previous assumption of gene-expression homogeneity within a tissue. The large quantity of data generated by this technology enables discoveries of cellular biology and disease mechanics that were previously not possible, and calls for accurate, scalable, and efficient processing pipelines. In this work, we propose SSCAE (spiking single-cell autoencoder), a novel SNN-based autoencoder for sc-RNA-seq dimensionality reduction. We apply this architecture to a variety of datasets, and the results show that it can match and surpass the performance of current state-of-the-art techniques. Moreover, the potential of this technique lies in its ability to be scaled up and to take advantage of neuromorphic hardware, circumventing the memory bottleneck that currently limits the size of sequencing datasets that can be processed.

Voice assistant applications have become omniscient nowadays. Two models that provide the two most important functions for real-life applications (i.e., Google Home, Amazon Alexa, Siri, etc.) are Automatic Speech Recognition (ASR) models and Speaker Identification (SI) models. According to recent studies, security and privacy threats have also emerged with the rapid development of the Internet of Things (IoT). The security issues researched include attack techniques toward machine learning models and other hardware components widely used in voice assistant applications. The privacy issues include technical-wise information stealing and policy-wise privacy breaches. The voice assistant application takes a steadily growing market share every year, but their privacy and security issues never stopped causing huge economic losses and endangering users' personal sensitive information. Thus, it is important to have a comprehensive survey to outline the categorization of the current research regarding the security and privacy problems of voice assistant applications. This paper concludes and assesses five kinds of security attacks and three types of privacy threats in the papers published in the top-tier conferences of cyber security and voice domain.

INTRODUCTION: Advances in wearable sensor technology have enabled the collection of biomarkers that may correlate with levels of elevated stress. While significant research has been done in this domain, specifically in using machine learning to detect elevated levels of stress, the challenge of producing a machine learning model capable of generalizing well for use on new, unseen data remain. Acute stress response has both subjective, psychological and objectively measurable, biological components that can be expressed differently from person to person, further complicating the development of a generic stress measurement model. Another challenge is the lack of large, publicly available datasets labeled for stress response that can be used to develop robust machine learning models. In this paper, we first investigate the generalization ability of models built on datasets containing a small number of subjects, recorded in single study protocols. Next, we propose and evaluate methods combining these datasets into a single, large dataset to study the generalization capability of machine learning models built on larger datasets. Finally, we propose and evaluate the use of ensemble techniques by combining gradient boosting with an artificial neural network to measure predictive power on new, unseen data. In favor of reproducible research and to assist the community advance the field, we make all our experimental data and code publicly available through Github at https://github.com/xalentis/Stress. This paper's in-depth study of machine learning model generalization for stress detection provides an important foundation for the further study of stress response measurement using sensor biomarkers, recorded with wearable technologies. METHODS: Sensor biomarker data from six public datasets were utilized in this study. Exploratory data analysis was performed to understand the physiological variance between study subjects, and the complexity it introduces in building machine learning models capable of detecting elevated levels of stress on new, unseen data. To test model generalization, we developed a gradient boosting model trained on one dataset (SWELL), and tested its predictive power on two datasets previously used in other studies (WESAD, NEURO). Next, we merged four small datasets, i.e. (SWELL, NEURO, WESAD, UBFC-Phys), to provide a combined total of 99 subjects, and applied feature engineering to generate additional features utilizing statistical summaries, with sliding windows of 25 s. We name this large dataset, StressData. In addition, we utilized random sampling on StressData combined with another dataset (EXAM) to build a larger training dataset consisting of 200 synthesized subjects, which we name SynthesizedStressData. Finally, we developed an ensemble model that combines our gradient boosting model with an artificial neural network, and tested it using Leave-One-Subject-Out (LOSO) validation, and on two additional, unseen publicly available stress biomarker datasets (WESAD and Toadstool). RESULTS: Our results show that previous models built on datasets containing a small number (<50) of subjects, recorded in single study protocols, cannot generalize well to new, unseen datasets. Our presented methodology for generating a large, synthesized training dataset by utilizing random sampling to construct scenarios closely aligned with experimental conditions demonstrate significant benefits. When combined with feature-engineering and ensemble learning, our method delivers a robust stress measurement system capable of achieving 85% predictive accuracy on new, unseen validation data, achieving a 25% performance improvement over single models trained on small datasets. The resulting model can be used as both a classification or regression predictor for estimating the level of perceived stress, when applied on specific sensor biomarkers recorded using a wearable device, while further allowing researchers to construct large, varied datasets for training machine learning models that closely emulate their exact experimental conditions. CONCLUSION: Models trained on small, single study protocol datasets do not generalize well for use on new, unseen data and lack statistical power. Machine learning models trained on a dataset containing a larger number of varied study subjects capture physiological variance better, resulting in more robust stress detection. Feature-engineering assists in capturing these physiological variance, and this is further improved by utilizing ensemble techniques by combining the predictive power of different machine learning models, each capable of learning unique signals contained within the data. While there is a general lack of large, labeled public datasets that can be utilized for training machine learning models capable of accurately measuring levels of acute stress, random sampling techniques can successfully be applied to construct larger, varied datasets from these smaller sample datasets, for building robust machine learning models.

The impact of device and circuit-level effects in mixed-signal Resistive Random Access Memory (RRAM) accelerators typically manifest as performance degradation of Deep Learning (DL) algorithms, but the degree of impact varies based on algorithmic features. These include network architecture, capacity, weight distribution, and the type of inter-layer connections. Techniques are continuously emerging to efficiently train sparse neural networks, which may have activation sparsity, quantization, and memristive noise. In this paper, we present an extended Design Space Exploration (DSE) methodology to quantify the benefits and limitations of dense and sparse mapping schemes for a variety of network architectures. While sparsity of connectivity promotes less power consumption and is often optimized for extracting localized features, its performance on tiled RRAM arrays may be more susceptible to noise due to under-parameterization, when compared to dense mapping schemes. Moreover, we present a case study quantifying and formalizing the trade-offs of typical non-idealities introduced into l-Transistor-l-Resistor (ITIR) tiled memristive architectures and the size of modular crossbar tiles using the CIFAR-10 dataset.

Oceanic temperature has a great impact on global climate and worldwide ecosystems, as its anomalies have been shown to have a direct impact on atmospheric anomalies. The major parameter for measuring the thermal energy of oceans is the sea surface temperature (SST). SST prediction plays an essential role in climatology and ocean-related studies. However, SST prediction is challenging due to the involvement of complex and nonlinear sea thermodynamic factors. To address this challenge, we design a novel ensemble of two stacked deep neural networks (DNNs) that uses air temperature, in addition to water temperature, to improve the SST prediction accuracy. To train our model and compare its accuracy with the state-of-the-art, we employ two well-known datasets from the national oceanic and atmospheric administration as well as the international Argo project. Using DNNs, our proposed method is capable of automatically extracting required features from the input time series and utilizing them internally to provide a highly accurate SST prediction that outperforms state-of-the-art models.

Neuromorphic computing is a promising technology that realizes computation based on event-based spiking neural networks (SNNs). However, fault-tolerant on-chip learning remains a challenge in neuromorphic systems. This study presents the first scalable neuromorphic fault-tolerant context-dependent learning (FCL) hardware framework. We show how this system can learn associations between stimulation and response in two context-dependent learning tasks from experimental neuroscience, despite possible faults in the hardware nodes. Furthermore, we demonstrate how our novel fault-tolerant neuromorphic spike routing scheme can avoid multiple fault nodes successfully and can enhance the maximum throughput of the neuromorphic network by 0.9%-16.1% in comparison with previous studies. By utilizing the real-time computational capabilities and multiple-fault-tolerant property of the proposed system, the neuronal mechanisms underlying the spiking activities of neuromorphic networks can be readily explored. In addition, the proposed system can be applied in real-time learning and decision-making applications, brain-machine integration, and the investigation of brain cognition during learning.

The cerebellum plays a vital role in motor learning and control with supervised learning capability, while neuromorphic engineering devises diverse approaches to high-performance computation inspired by biological neural systems. This article presents a large-scale cerebellar network model for supervised learning, as well as a cerebellum-inspired neuromorphic architecture to map the cerebellar anatomical structure into the large-scale model. Our multinucleus model and its underpinning architecture contain approximately 3.5 million neurons, upscaling state-of-the-art neuromorphic designs by over 34 times. Besides, the proposed model and architecture incorporate 3411k granule cells, introducing a 284 times increase compared to a previous study including only 12k cells. This large scaling induces more biologically plausible cerebellar divergence/convergence ratios, which results in better mimicking biology. In order to verify the functionality of our proposed model and demonstrate its strong biomimicry, a reconfigurable neuromorphic system is used, on which our developed architecture is realized to replicate cerebellar dynamics during the optokinetic response. In addition, our neuromorphic architecture is used to analyze the dynamical synchronization within the Purkinje cells, revealing the effects of firing rates of mossy fibers on the resonance dynamics of Purkinje cells. Our experiments show that real-time operation can be realized, with a system throughput of up to 4.70 times larger than previous works with high synaptic event rate. These results suggest that the proposed work provides both a theoretical basis and a neuromorphic engineering perspective for brain-inspired computing and the further exploration of cerebellar learning.

The unpredictability of seizures continues to distress many people with drug-resistant epilepsy. On account of recent technological advances, considerable efforts have been made using different hardware technologies to realize smart devices for the real-time detection and prediction of seizures. In this paper, we investigate the feasibility of using Memristive Deep Learning Systems (MDLSs) to perform real-time epileptic seizure prediction on the edge. Using the MemTorch simulation framework and the Children's Hospital Boston (CHB)-Massachusetts Institute of Technology (MIT) dataset we determine the performance of various simulated MDLS configurations. An average sensitivity of 77.4% and a Area Under the Receiver Operating Characteristic Curve (AUROC) of 0.85 are reported for the optimal configuration that can process Electroencephalogram (EEG) spectrograms with 7,680 samples in 1.408ms while consuming 0.0133W and occupying an area of 0.1269mm2in a 65nm Complementary Metal-Oxide-Semiconductor (CMOS) process.

Health professionals extensively use Two-Dimensional (2D) Ultrasound (US) videos and images to visualize and measure internal organs for various purposes including evaluation of muscle architectural changes. US images can be used to measure abdominal muscles dimensions for the diagnosis and creation of customized treatment plans for patients with Low Back Pain (LBP), however, they are difficult to interpret. Due to high variability, skilled professionals with specialized training are required to take measurements to avoid low intra-observer reliability. This variability stems from the challenging nature of accurately finding the correct spatial location of measurement endpoints in abdominal US images. In this paper, we use a Deep Learning (DL) approach to automate the measurement of the abdominal muscle thickness in 2D US images. By treating the problem as a localization task, we develop a modified Fully Convolutional Network (FCN) architecture to generate blobs of coordinate locations of measurement endpoints, similar to what a human operator does. We demonstrate that using the TrA400 US image dataset, our network achieves a Mean Absolute Error (MAE) of 0.3125 on the test set, which almost matches the performance of skilled ultrasound technicians. Our approach can facilitate next steps for automating the process of measurements in 2D US images, while reducing inter-observer as well as intra-observer variability for more effective clinical outcomes.

Hardware implementation of functional neuronal circuits has rapidly become more feasible due to increasing reliability of memristor-CMOS integration at a scale necessitated by neuromorphic processes. Most neuromorphic implementations of the memristor treat it as a variable synaptic weight modulated by conductance. The work in this paper enhances biological plausibility of analog vision system circuits by mimicking the nonlinear dynamics of a network of receptive field that resembles those found in the lateral geniculate nucleus. The memristive circuit provides a biologically accurate response where a single cell behaves simultaneously as its own on-center receptive field, and as the off-surround receptive field of adjacent cells. It maximally responds to spatial variations of light. Each output is a fundamental unit of cortical visual information, and we show how the receptive field of each neuron can be superimposed to perceive edges and recognize objects when scaled to higher cortical areas. The functionality of the array is verified in SPICE simulations.

Summary form only given. This paper proposes a neuromorphic platform for on-FPGA online Spike Timing Dependant Plasticity (STDP) learning, based on the COordinate Rotation DIgital Computer (CORDIC) algorithms. The implemented platform comprises two main components. First, the Izhikevich neuron model is modified for implementation using the CORDIC algorithm, simulated to ensure the model accuracy, described as hardware, and implemented on FPGA. Second, the STDP learning algorithm is adapted and optimized using the CORDIC method, synthesized for hardware, and implemented to perform on-FPGA online learning on a network of CORDIC Izhikevich neurons to demonstrate competitive Hebbian learning. The implementation results are compared with the original model and state-of-the-art to verify accuracy, effectiveness, and higher speed of the system. These comparisons confirm that the proposed neuromorphic system offers better performance and higher accuracy while being straightforward to implement and suitable to scale.

In Low-Power and High-Speed Deep FPGA Inference Engines for Weed Classification at the Edge [1] we implemented GPU- and FPGA-accelerated deterministically binarized Deep Neural Networks (DNNs), tailored toward weed species classification for robotic weed control. The dataset used consisted of 17,508 unique 256×256 color images in 9 classes, collected in situ from eight rangeland areas across Northern Australia [2]. For this live demonstration, we have designed a weed classification game. We first provide the visitor with a printed sheet showing several examples of each of the 9 various weed species classes in our dataset, to learn and memorize the weed names. This learning process can take for as long as the visitor wishes. For the game to start, five weed images from our test set are randomly selected. We then measure the interference times and accuracies for our optimized GPUand FPGA-accelerated binarized DNNs, alongside the visitors' performance. Are low-resolution, low-power, binarized DNNs able to outperform humans at categorizing weed species?

Memristive devices arranged in cross-bar architectures have shown great promise to facilitate the acceleration and improve the power efficiency of Deep Learning (DL) systems for deployment in resource-constrained platforms, such as the Internet-of-Things (IoT) edge devices. These cross-bar architectures can be used to implement various in-memory computing operations, such as Multiply-Accumulate (MAC) and convolution, which are used extensively in Deep Neural Networks (DNNs) and Convolutional Neural Networks (CNNs). Currently, there is a lack of an open source, general, high-level simulation platform that can fully integrate any behavioral or experimental memristive device model into cross-bar architectures. This paper presents such a framework named MemTorch, which integrates directly with the well-known PyTorch Machine Learning (ML) library. To demonstrate an example practical use of MemTorch, we use it to simulate the performance degradation that non-ideal devices introduce to a typical Memristive DNN (MDNN) implementing VGG-16 for CIFAR-10. Our open source1MemTorch framework can be used by circuit and system designers to conveniently build customized large-scale simulation platforms, as a preliminary step before circuit-level realization.

While hardware implementations of inference routines for Binarized Neural Networks (BNNs) are plentiful, current realizations of efficient BNN hardware training accelerators, suitable for Internet of Things (IoT) edge devices, leave much to be desired. Conventional BNN hardware training accelerators perform forward and backward propagations with parameters adopting binary representations, and optimization using parameters adopting floating or fixed-point real-valued representations-requiring two distinct sets of network parameters. In this paper, we propose a hardware-friendly training method that, contrary to conventional methods, progressively binarizes a singular set of fixed-point network parameters, yielding notable reductions in power and resource utilizations. We use the Intel FPGA SDK for OpenCL development environment to train our progressively binarizing DNNs on an OpenVINO FPGA. We benchmark our training approach on both GPUs and FPGAs using CIFAR-10 and compare it to conventional BNNs.

Stochastic Computing (SC) presents a low-cost and low-power alternative to conventional binary computing. In SC, continuous values are represented by stochastically generated bit streams. By performing simple hardware-friendly bit-wise operations on these streams, complex calculations can be realized very efficiently. However, the inherent randomness and approximation used in SC can result in undesirable computational errors. As Convolutional Neural Networks (CNNs) are inherently error-tolerant, SC could be embedded in them to gain higher speed and lower power without significant accuracy loss. In this paper, we propose using SC techniques to approximate multiplication operations on fixed-point weights and biases during training of CNNs. By employing such techniques, we demonstrate near state-of-the-art learning performance for the MNIST and CIFAR-10 datasets, while achieving significant resource and speed improvements when implementing the deep networks on a Field Programmable Gate Array (FPGA). For MNIST, we demonstrate that SC compared to conventional computing, will result in almost 3 times increase in learning speed with only 1.37% degradation in validation accuracy. Similarly, for CIFAR-10, training is accelerated 3.5 times with a degradation of 3.39%. We also show that our FPGA implementations of CNNs adopting stochastic multipliers consume over 17 times less power than their GPU counterparts.

For this demonstration, we have implemented a Spiking Neural Network (SNN) on a Field Programmable Gate Array (FPGA) and trained it using Spike Timing Dependent Plasticity (STDP) to identify temporally encoded characters, in an unsupervised manner. The constructed one-layer network consists of plastic excitatory and non-plastic inhibitory synapses, which are connected to output Izhikevich neurons. The implemented neural hardware demonstrates a powerful and fast learning scheme, which brings about a significant unsupervised classification accuracy of 94 %.

Neuromorphic hardware platforms have demonstrated significant promise in cognitive tasks such as visual processing and classification. These platforms usually consist of several layers of spiking neurons for feature extraction and various learning mechanisms, which renders the associated networks power and hardware hungry. In this paper, we have implemented a simplified proof-of-concept Spiking Neural Network (SNN) on a Field Programmable Gate Array (FPGA) and trained it using Spike Timing Dependent Plasticity (STDP) to identify temporally encoded characters, in an unsupervised manner. The constructed one-layer network consists of excitatory synapses, which receive input characters in the form of Poissonian spike trains from the pre-synaptic side. From the post-synaptic side, the synapses are connected to output Izhikevich neurons. In addition, non-plastic inhibitory synapses between the output neurons are introduced to implement lateral inhibition and competitive learning. The implemented neural hardware demonstrates a powerful and fast learning scheme, which brings about a significant unsupervised classification accuracy of 94 %. In addition, since the proposed network receives the characters in the form of spike trains, it is amenable to being interfaced to neuromorphic event-driven sensors such as silicon retina, making the proposed platform useful for online unsupervised template matching applications.

Hardware implementations of spiking neural networks offer promising solutions for computational tasks that require compact and low-power computing technologies. As these solutions depend on both the specific network architecture and the type of learning algorithm used, it is important to develop spiking neural network devices that offer the possibility to reconfigure their network topology and to implement different types of learning mechanisms. Here we present a neuromorphic multi-neuron VLSI device with on-chip programmable event-based hybrid analog/digital circuits; the event-based nature of the input/output signals allows the use of address-event representation infrastructures for configuring arbitrary network architectures, while the programmable synaptic efficacy circuits allow the implementation of different types of spike-based learning mechanisms. The main contributions of this article are to demonstrate how the programmable neuromorphic system proposed can be configured to implement specific spike-based synaptic plasticity rules and to depict how it can be utilised in a cognitive task. Specifically, we explore the implementation of different spike-timing plasticity learning rules online in a hybrid system comprising a workstation and when the neuromorphic VLSI device is interfaced to it, and we demonstrate how, after training, the VLSI device can perform as a standalone component (i.e., without requiring a computer), binary classification of correlated patterns.

The ability to carry out signal processing, classification, recognition, and computation in artificial spiking neural networks (SNNs) is mediated by their synapses. In particular, through activity-dependent alteration of their efficacies, synapses play a fundamental role in learning. The mathematical prescriptions under which synapses modify their weights are termed synaptic plasticity rules. These learning rules can be based on abstract computational neuroscience models or on detailed biophysical ones. As these rules are being proposed and developed by experimental and computational neuroscientists, engineers strive to design and implement them in silicon and en masse in order to employ them in complex real-world applications. In this paper, we describe analog very large-scale integration (VLSI) circuit implementations of multiple synaptic plasticity rules, ranging from phenomenological ones (e.g., based on spike timing, mean firing rates, or both) to biophysically realistic ones (e.g., calcium-dependent models). We discuss the application domains, weaknesses, and strengths of various representative approaches proposed in the literature, and provide insight into the challenges that engineers face when designing and implementing synaptic plasticity rules in VLSI technology for utilizing them in real-world applications.

Spike Timing Dependent Plasticity (STDP) is a time-based synaptic plasticity rule that has generated significant interest in the area of neuromorphic engineering and Very Large Scale Integration (VLSI) circuit design. During the last decade, STDP and STDP-like learning mechanisms have shown promising solutions for various real world applications, ranging from pattern recognition to robotics. This paper presents a novel analog VLSI model for STDP that possesses advantages compared to previously published VLSI STDP designs. The presented STDP circuit is capable of reproducing the outcomes of several well known experiments using various plasticity rules inducing STDP protocols that utilise pairs, triplets, and quadruplets of spike patterns. When the circuit is compared to state-of-the-art VLSI STDP circuits, it shows a compact and symmetric design that makes the proposed circuit a powerful component for use in designing STDP or time-based Hebbian learning experiments and applications.

The Bienenstock-Cooper-Munro (BCM) and Spike Timing-Dependent Plasticity (STDP) rules are two experimentally verified form of synaptic plasticity where the alteration of synaptic weight depends upon the rate and the timing of pre- and post-synaptic firing of action potentials, respectively. Previous studies have reported that under specific conditions, i.e. when a random train of Poissonian distributed spikes are used as inputs, and weight changes occur according to STDP, it has been shown that the BCM rule is an emergent property. Here, the applied STDP rule can be either classical pair-based STDP rule, or the more powerful triplet-based STDP rule. In this paper, we demonstrate the use of two distinct VLSI circuit implementations of STDP to examine whether BCM learning is an emergent property of STDP. These circuits are stimulated with random Poissonian spike trains. The first circuit implements the classical pair-based STDP, while the second circuit realizes a previously described triplet-based STDP rule. These two circuits are simulated using 0.35 µm CMOS standard model in HSpice simulator. Simulation results demonstrate that the proposed triplet-based STDP circuit significantly produces the threshold-based behaviour of the BCM. Also, the results testify to similar behaviour for the VLSI circuit for pair-based STDP in generating the BCM.

Spike-Timing Dependent Plasticity (STDP) is believed to play an important role in learning and the formation of computational function in the brain. The classical model of STDP which considers the timing between pairs of pre-synaptic and post-synaptic spikes (p-STDP) is incapable of reproducing synaptic weight changes similar to those seen in biological experiments which investigate the effect of either higher order spike trains (e.g. triplet and quadruplet of spikes) [1]-[3], or, simultaneous effect of the rate and timing of spike pairs [4] on synaptic plasticity. In this paper, we firstly investigate synaptic weight changes using a p-STDP circuit [5] and show how it fails to reproduce the mentioned complex biological experiments. We then present a new STDP VLSI circuit which acts based on the timing among triplets of spikes (t-STDP) that is able to reproduce all the mentioned experimental results. We believe that our new STDP VLSI circuit improves upon previous circuits, whose learning capacity exceeds current designs due to its capability of mimicking the outcomes of biological experiments more closely; thus plays a significant role in future VLSI implementation of neuromorphic systems.

Multiprocessor task scheduling plays a fundamental role in parallel applications and distributed networks. All of the methods for this kind of scheduling are concerned with achieving optimal running time. In this way parallel execution of tasks on several processors based on precedence graph should