We present the status and direction of silicon semiconductor technologies targeted for applications such as wireless, networking, instrumentation, and storage markets. Various technological aspects for multiple branches of RF foundry technologies that are based on the standard foundry compatible CMOS node are discussed - SiGe BiCMOS HP ("high performance") tailored to high-frequency applications, SiGe BiCMOS WL ("cost performance") tailored to wireless/storage applications, and RF-CMOS optimized for low-cost consumer applications. Future opportunities and challenges for advancement in RF technologies are described in light of CMOS and SiGe heterojunction bipolar transistor scaling. In addition, we discuss the maturity of SiGe BiCMOS by looking at the levels of integration and manufacturability.

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

The tremendous demand for advanced microprocessors is making developers offer a superior product at a competitive price which meets specific performance, power, and reliability requirements. Today's products are designed and built with essentially the same design, fabrication, and test tools used by all industry manufacturers and are constrained by the same device physics, package impedance, heat dissipation capability, and battery energy density limitations. In addition, the current technology generation presents a new set of difficult challenges for the treatment of power dissipation. Lowering voltage to reduce power diminishes FET overdrive and the performance of the device. Recapturing performance by migrating quickly to the next scaled technology generation, however, makes low-power designs expensive, and is not always necessary. Standard full scaling preserves physical and electrical relationships between parameters. On the other hand, selective scaling of specific device parameters may allow the exploitation of existing tools and designs by the use of a different design point on the process "surface". This paper describes recent attempts to explore the feasibility of selective scaling and anticipated constraints associated with future technology generations.