Deep neural networks (DNNs) have gained significant attention due to the rapid growth of learning-based applications. However, the computational demands of DNNs limit their performance in many of these applications. As a result, extensive research has focused on hardware implementations of these networks as accelerators. Array-based accelerators are an efficient architecture type that employs an array of processing elements (PEs) for parallel computations. However, array-based accelerators cannot reach their potential performance due to having fixed dimensions to execute different layers of DNNs. This article proposes a reconfigurable architecture to address this limitation by adaptively selecting the size of PEs to better align with the dimensions of the active DNN layers. Simulations demonstrate significant improvements for various DNN models compared to state-of-the-art architectures. Experimental results show that the proposed architecture achieves, on average, 43% higher speed, 32% more resource utilization, and a 38% reduction in on-chip memory access rate compared to the baseline architecture when executing GoogLeNet model layers. These enhancements are achieved with only a 1.6% area overhead, making the proposed architecture a cost-effective design. Furthermore, by incorporating multithreading into the simulator's source code, we significantly accelerate simulations compared to the basic version.

This is a corrigendum for the article "RADI: A High-Performance Reconfigurable Array-Based Accelerator for DNN Implementations" published in ACM Trans. Des. Autom. Electron. Syst. 31, 5, Article 116 (April 2026), 27 pages.

The reliability is a vital aspect in the design of Network-on-Chip (NoC) based systems because a fault in communication medium may cause an overall system failure. On the other hand, performance degradation is an inescapable consequence of fault-tolerant architectures. In this paper, we propose a fault-tolerant NoC architecture that attains higher performance by using low cost agents in a hierarchical manner. These agents which are distributed all over the network, collect, process, and distribute different fault information. Moreover, we propose an enhanced fault-tolerant and congestion-aware routing method that exploits the classified fault information related to the permanent faults that might occur inside the links, network interfaces and different parts of the routers. The experimental results reveal that the proposed NoC architecture imposes small area and power overheads.

This paper presents performance and reliability evaluation of deterministic and adaptive fault-tolerant routing algorithms used in Network-on-Chip (NoC) designs. The investigated methods have a multi-level fault-tolerance capability and therefore can be separately evaluated. To illustrate the effectiveness of these methods, we conduct appropriate simulations on different applications for performance evaluation. But, for reliability assessment, we propose an analytical approach based on combinatorial reliability models to show the effect of fault-tolerant routing algorithms on overall NoC reliability.

This paper presents a fault-tolerant routing algorithm for mesh-based Networks-on-Chip (NoC) with faulty links. It is a distributed, adaptive and congestion-aware routing algorithm where only two virtual channels are used for both adaptiveness and fault-tolerance. The proposed routing method has a multilevel fault-tolerance capability and therefore it is capable to tolerate more faulty links in more complicated faulty situations with additional hardware costs. The network performance, fault-tolerance capability and hardware overhead are evaluated through appropriate simulations. The experimental results show that the overall reliability of a Network-on-Chip is significantly enhanced against multiple link failures or partially faulty routers with only a small hardware overhead.

This paper presents a very low cost routing method to tolerate faulty links and routers in mesh-based Networks-on-Chip (NoC). With reconfigurability, this new algorithm supports irregular topologies caused by faulty components in a network. It concurrently uses both fault and congestion information to route the packets by utilizing only two virtual channels for both fault-tolerance and adaptivity. This method has a multi-level fault-tolerance capability and therefore it is capable to tolerate more faulty components with additional costs. Its performance and overhead are evaluated through appropriate simulations and syntheses. The experimental results show that a significant reliability improvement is achieved against multiple component failures with only a few percent area and power overheads.