As the complexity of analog circuit optimization problems increases, existing optimization algorithms struggle with intricate circuit specifications. In this paper, we propose a hybrid multi-population evolutionary algorithm framework that integrates and enhances GA, DE, and PSO. We introduce a dynamic fitness function to address multi-constraint, multi-objective problems, and design a beta-distribution-based crossover operator with grouping to handle correlations between design variables and the highly nonlinear, locally sensitive nature of circuit metrics. Additionally, we implement an asymmetric crowding mechanism that considers nominal variables to maintain population diversity and develop a multi-population cooperation strategy to improve both convergence speed and solution quality. Our framework is validated on four analog circuits: a Low Dropout Regulator, a Two-Stage Amplifier, a Four-Stage Amplifier, and a Rail-to-rail Class AB Amplifier. Results demonstrate that our algorithm achieves faster convergence and superior solutions, leading to better performance of analog circuits and significant improvements in key multi-objective metrics such as hypervolume (HV) and dominance coverage. These confirm the effectiveness and efficiency of the proposed framework in solving complex analog circuit optimization problems.

Compute-in-memory (CIM) has emerged as a prominent research focus in recent years, offering a promising alternative for advancing traditional von Neumann architecture computers. However, the extensive array structures and peripheral circuits inherent in CIM introduce challenges related to latency and power consumption. The operation unit (OU) has gained attention as a practical solution to these issues, significantly transforming the computational paradigm of in-memory computing. Despite its potential, the possibilities enabled by this approach remain underexplored. This article presents a novel architecture, single-pass, designed around OU implementation with a new OU partitioning method optimized for sparse networks. Additionally, we propose a matrix compression technique leveraging a dual heuristic greedy algorithm (DHGA), forming the foundation of our architecture-specific mapping strategy. Experimental results demonstrate that, within given area constraints, our architecture achieves an average energy efficiency improvement of 29.8% and a speedup of 82.3% across various networks compared to the baseline.

Sine/cosine (SC) is widely used in practical engineering applications, such as image compression and motor control. Nevertheless, due to power sensitivity and speed demands, SC acceleration suffers from limitations in traditional von-Neumann architectures. To overcome this challenge, we propose accelerating SC and convolution using a static random access memory (SRAM)-based in-memory computing (IMC) architecture through an algorithm-architecture co-optimization manner. We develop the first SC algorithm that transforms nonlinear operations into the IMC paradigm, enabling IMC array to handle both SC and artificial intelligence (AI) tasks and making the IMC array a reusable module. Our architecture extends computing functions of macro dedicated to convolutional neural networks (CNNs), with less than a 1% area increase. The proposed SC algorithm for FP32 data achieves high accuracy within 1 unit in the least significant place (ulp) error margin compared withCmath library. Moreover, we build an intelligent IMC system that supports various CNNs. Our IMC macro implements 512-kb binary weight storage within 3.0366-mm2area in SMIC 28-nm technology and presents area/energy efficiency of 2160.29–270.04 GOPS/mm2and 513.95–8.03 TOPS/W in CNN mode. The proposed algorithm and architecture facilitate the integration of more nonlinear functions into IMC with minimal area overhead.

To address the complex nonlinear problem of determining class-F voltage-controlled oscillator (VCO) dimensions, this article introduces an electronic design automation (EDA) framework that rapidly optimizes multiple design objectives yielding superior outcomes. The framework incorporates fast frequency determination, harmonic alignment, and extremal optimization of multiobjective particle swarm optimization with crowding distance (FHE-MOPSO-CD), an efficient algorithm we developed specifically for class-F VCOs, which includes transformer-based tank circuit strategies and extremum optimization techniques. Using a 55-nm CMOS process, this algorithm optimized various class-F VCO topologies, achieving excellent metrics and confirming its versatility. Optimization results indicate that at a 10-MHz offset, the figure of merit (FoM) is at least 8.81 dBc/Hz higher than values reported in the literature. Compared with other analog/RF dimension optimization methods, our approach yielded a higher hypervolume, indicating better convergence and greater diversity of solutions.