The focus of this paper is to demonstrate first that high order noise shaped data converters can be digitally generated in open loop architectures, avoiding both stability problems and complex analog loops, and second that a low power PLL design can be used as the clock generator for such VCO-based ADCs. An open-loop 2nd-order VCO-based ADC is proposed by means of a digital approximation of the pulse shaping filter to a second-order sinc function. The pulse shaping filter is digitized with a time reference signal used to quantize time differences and taken from a low power PLL implemented on silicon using a 65nm CMOS design node. The proposed architecture is firstly described theoretically and afterwards is experimentally tested for an audio bandwidth application. A model of the PLL output phase noise is measured in the test chip and is used in a simulation platform to check the real performance that could be experimentally achieved. The results prove that the time reference requirements can be met with low power architectures, achieving negligible SNR degradation and opening up the possibility of implementing scalable, low power and small area all-digital Nth-order VCO-based ADCs.

A multi-stage, open-loop Current Controlled Oscillator (CCO)-based Analog-to-Digital Converter (ADC) is proposed for non-linearity compensation and enhanced noise shaping. This architecture consists of multiple CCO-based stages connected in a cascading manner. The digital outputs of these stages are skillfully combined through digital filters to both compensate for the distortion of the CCOs and increase the noise shaping order. We present an application example with three stages, demonstrating a significant reduction in distortion, particularly from the first stage, and a notable improvement in Signal-to-Noise and Distortion Ratio (SNDR) performance when compared to first-order structures.

Digital sensors contain reconfigurable Sigma-Delta modulators that support different working modes. Depending on the timing of reconfiguration, high amplitude transients may appear at the sensor output. This article analyzes the transient response of discrete time Sigma-Delta modulators to find the optimal reconfiguration moment. It is shown that the transient is optimal when the first state variable of the loop filter is zero at the reprogramming instant. The optimal time is predicted with a pulse frequency modulator model. Finally, a set of general equations are given to predict the transient sequence for any modulator order and topology.

This paper presents a novel approach to analyze clock jitter influence in the performance of continuous-time sigma-delta modulators. The analysis is based on projecting all the signals and operations over an artificial time-base relative to the sampling clock, on which the sampling period can be considered constant. In the proposed time-base, clock jitter can be modeled as the modulation of the input signal frequency and the integrators gain. Unlike standard techniques, we do not rely on the feedback pulse properties, which enables a broader application of our technique to band-pass or VCO-based sigma-delta modulators. In this paper, we present the basic theory of this technique and its application to some practical examples, showing a good matching between prediction and numerical simulation.

The parallelism between a first-order sigma-delta modulator and a VCO-based ADC allows to calculate the DFT of the sigma delta sequence using Pulse Frequency Modulation theory. This paper exploits this parallelism to propose a more general model that links continuous time sigma delta modulators of an arbitrary order with Pulse Frequency Modulators. This novel point of view also predicts the spectral contents of a sigma delta encoded sequence beyond the white quantization noise model. The quantization noise can be split in two components, a deterministic one representing the carrier harmonic sidebands of a Pulse Frequency Encoded signal and a noise shaped pseudorandom signal representing the sampling operation. We seize these findings to propose a conjecture on the stability of a sigma delta modulator.

Single-bit ΣΔ modulators are prone to exhibit idle tones in stable operation. In audio applications the human hear can perceive this tonal behavior degrading the quality of the application. Classical solutions to overcome this problem are the use of dithering signals or chaotic modulators. In this work we compare these methods with the addition of a Fractional Delay FIR filter. The proposed technique is analyzed in terms of NTF modification and complexity, as well as the effectiveness of the technique in reducing high frequency idle tones; the impact on the modulator performance is also studied.

This paper shows how to enhance the resolution of a VCO based ADC by transforming a ring oscillator into a continuous-time maximum length sequence generator. The code spreading provided by the maximum length sequence can be decoded after sampling by a look up table. Compared to an M tap ring oscillator, an equivalent maximum length sequence generator enhances the resolution of the resulting ADC by a factor 2M/M. We derive the basic system analysis for this new ADC architecture and show a simulation example.

High-resolution noise shaping ADCs are increasingly used in measurement of biopotential signals. This paper presents a novel low power low voltage ADC based on a Dual-Slope (DS) integrating quantizer. To reduce power consumption, the active RC integrator used in integrating quantizers has been replaced by a passive RC low pass filter. Hence, no operational amplifiers are needed. This simplification implies two drawbacks. The passive integrator limits noise shaping due to imperfect integration. Moreover, approximation of linear ramps by an exponential capacitor charge introduces distortion. This paper reveals that the most limiting factor is distortion instead of imperfect integration. A simple method is proposed to compensate the distortion.

We present a multi-stage noise shaping modulator that uses a continuous time first stage and a Gated Ring Oscillator (GRO)as second stage. A Pulse Width Modulator (PWM) and a Time-to-Digital converter (TDC) is used as time-based quantizer in first stage. The binary output of the PWM is reused to control the GRO, avoiding the distortion that would be introduced by a conventional VCO. The digital outputs of both stages are filtered out to remove first stage quantization noise as in any conventional multi-stage Sigma-Delta Architecture. The architecture is suitable to extend the bandwidth or the resolution of a low oversampling time-based Continuous Time Sigma-Delta Modulators (CTIAM) with a small amount of analog circuitry and low power consumption. A simulation example using a 2-1 architecture, 50MHz bandwidth and 2GHZ clock is presented, showing 76dB SNDR at system level.

This paper presents a new approach to reduce the out of band energy in a class D amplifier driven by a DAC. The proposed architecture is based on a Time Encoded Filter (TEF). The TEF operates as a discrete time linear system on the pulse widths of a PWM signal rather than on the amplitudes of a sequence. It only requires RC circuits, comparators and digital logic. Hence, it can be integrated along with the D/A converter. The main advantage of this approach is that the number of power inductors and capacitors of the off chip low pass filter may be reduced.

This work presents a design procedure for Continuous Time (CT) Cascade Sigma Delta Modulators (SDMs) using the Sturdy approach for Discrete Time Modulators, where the usual Digital Cancellation Filters are removed. The error cancellation mechanism is affected by excess loop delay in the CT approach. Special design considerations are derived and a specific design methodology is proposed. A 10-MHz bandwidth and 80-dB peak SNR example is designed and simulated using a 2-1 topology.

This paper proposes a technique to spectrally shape the clock jitter noise that is contributed by the feedback DACs in a continuous time sigma-delta modulator. A mathematical model and a simulation example are presented, showing a first-order shaping of the jitter noise