Next generation wireless communications such as B5G (Beyond 5G)/6G and wireless LAN are expected to support sensing function in addition to broadband wireless access to support new applications, and radar-communication integration is becoming a hot topic nowadays. This paper compares radar communication integration approaches, i.e. FMCW (Frequency Modulated Continuous Wave) radar-based, OFDM (Orthogonal Frequency Division Multiplexing) radar-based and PMCW (Pulse Modulation Continuous Wave) radar-based approach, and proposes radar-communication integration system based on PMCW radar using Zadoff-Chu sequence which is CAZAC (Constant Amplitude Zero Auto Correlation) sequence, i.e. constant amplitude and zero auto correlation, suitable for PMCW radar applications. This paper describes basic design issues such as signal format, maximum detection range and range resolution and shows correlation detection performance of the proposed PMCW radar when filtering is applied.

High definition television (HDTV) is expected to be one of the major services offered in future broadband integrated services digital networks (B-ISDN). Transmitting HDTV signals over digital networks requires sophisticated compression techniques to limit bit-rate requirements and to provide high-quality, reliable services to customers. To transmit image signals within a studio and between studios or broadcasting stations, multiple encoding and decoding of signals without visible degradation is required. The authors describe a high-quality HDTV codec that can encode original 1.2 Gb/s HDTV signals at 600 Mb/s. A subband DPCM (differential pulse-code modulation) coding algorithm capable of distortion-free encoding is used. Input signals are decomposed into four bands in the horizontal and vertical directions. A new architecture of perfect reconstructive short-kernel subband filters that reduces subband signal entropy has been adopted. Three bands are coded with adaptive DPCM and one band is coded with PCM. The performance of the codec is evaluated using true video signals. Experimental results show that a very high percentage of samples of component signals can be transmitted distortion free. A signal-to-noise ratio (SNR) of over 45 dB is obtained with signals transmitted after the quantization process. Degradation after nine encoding and decoding processes is only 2 dB in terms of SNR.>

A dynamic load balancing method is proposed that uses a multistage switching network to solve the problem of load concentration on certain processors for video coding in multiprocessor digital signal processors. (DSPs) This method balances the processing load by distributing the total load among the processor elements having smaller loads. The load distribution is performed by the multistage switching network, which transmits the load quantity information within the network. A scheduling method for a motion picture coding algorithm using multiprocessor DSPs is also proposed. This scheduling method takes full advantage of the multistage switching network functions when distributing the processing load and sorting the processed results. By using computer simulation, multiprocessor DSP performance with the proposed method is shown to be double that of a conventional multiprocessor DSP when an initially unbalanced load is allocated to the processors, as in picture coding for TV conferences.>

An LSI-based user-network interface circuit, applicable to a network terminal (NT) for the integrated services digital network (ISDN) basic interface is developed. Adaptive timing extraction, with a simplified polyphase phase-locked oscillator, is introduced into the circuit for application to both point-to-point and passive bus configurations. This circuit does not require any manual adjustment. In addition to the primitives defined by CCITT between layers one and two, a new primitive is adopted for controlling the transmission of information. This primitive avoids premature transmission due to processing delays in the exchange terminal (ET). The above functions are fabricated on a CMOS gate-array LSI chip with 4000 gates. The performance of the interface circuit is confirmed with special attention to transmission and electrical characteristics.>

A new polyphase phase-locked oscillator (P-PLO) is proposed which overcomes one of the greatest difficulties in the passive bus configuration: timing extraction from signals in multiplexed channels with different mean phases. The proposed oscillator generates appropriate retiming clock pulses for each channel independent of other channels. Moreover, since pulse overlaps between channels may appear at the first and last bits of each channel, the oscillator shifts retiming clock phases of these bits to avoid sampling overlaps. A performance analysis method extended from the conventional Markov chain model is also proposed. The theoretically obtained jitter and retiming margin characteristics correspond closely to experimental results. This circuit is also shown to be adaptable to point-to-point configurations which, like passive bus, will be used in the ISDN basic interface recommended as one of the 1-series interfaces by CCITT. This allows easy rearrangement of interface wiring, e.g., changing from the passive bus to point-to-point configuration, without any adjustment of the network terminator.