Filling high aspect ratio trenches is an essential manufacturing step for state of the art memory cells. Understanding and simulating the transport and surface processes enables one to achieve voidless filling of deep trenches, to predict the resulting profiles, and thus to optimize the process parameters and the resulting memory cells. Experiments on arsenic doped polysilicon deposition show that under certain process conditions step coverages greater than unity can be achieved. We developed a new model for the simulation of arsenic doped polysilicon deposition, which takes into account surface coverage dependent sticking coefficients and surface coverage dependent arsenic incorporation and desorption rates. The additional introduction of Langmuir-Hinshelwood type time dependent surface coverage enabled the reproduction of the bottom up filling of the trenches in simulations. Additionally, the rigorous treatment of the time dependent surface coverage allows to trace the in situ doping of the deposited film. The model presented was implemented and simulations were carried out for different process parameters. Very good agreement with experimental data was achieved with theoretically deduced parameters. Simulation results are shown and discussed for polysilicon deposition into 0.1 /spl mu/m wide and 7 /spl mu/m deep, high aspect ratio trenches.

For wafer sizes in state of-the-art semiconductor manufacturing ranging up to 300 mm, the uniformity of processes across the wafer becomes a very important issue. We present a fully three-dimensional model for the feature scale simulation of continuum transport and reaction determined high-pressure chemical vapor deposition processes suitable for the investigation of such nonuniformities. The newly developed three-dimensional approach combines topography simulation, meshing, and finite element method tools, and allows simulations over arbitrary geometries such as structures resulting from nonuniform underlying physical vapor deposition films. This enables the examination of film profile variations across the wafer for multistep processes consisting of low- and high-pressure parts such as Ti/TiN/W plug-fills, Additionally, the model allows a very flexible formulation of the involved gas chemistry and surface reactions and can easily be extended to process chemistries including gas phase reactions of precursors as observed in deposition of silicon dioxide from tetraethylorthosilicate (TEOS). We show simulation examples for a tungsten deposition process, which is applied as last step in a Ti/TiN/W plug-fill. For filling of an L-shaped trench, we show the transition from transport to reaction limited process conditions.

Integrated circuits have evolved to a stage where interconnections significantly limit their performance and functional complexity. We introduce a set of tools to perform highly accurate three-dimensional capacitance and resistance/thermal calculations of interconnect structures. We automatically generate these structures from layout information and a given process description. The main enhancement of our work is that we extract the interconnect characteristics after a complete and accurate topography simulation with previous optional lithography analysis, instead of elementary geometric blocks derived from simple analytical models. The capacitance and resistance/thermal extractor simulators are based on optimized finite-element methods, and the topography simulators use a cellular data-based approach.