EDBT 2026 Demo / reviewers in the wild / expert
DaeGon Kim
dblp:76/4634
· DBLP profile ↗
5ranked-venue papers
2as first author
0since 2021 · last 2012
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-authorSoftware engineering, systems software and programming languages · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
3 papers |
Compilers and program optimization · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Parallel and multicore computing · 100% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization
code generation |
0.2 | 2 | 2012 | Parameterized loop tiling · ACM Trans. Program. Lang. Syst. 2012 Parameterized tiled loops for free · PLDI 2007 |
Compilers and program optimization
loop optimization |
0.2 | 2 | 2012 | Parameterized loop tiling · ACM Trans. Program. Lang. Syst. 2012 Parameterized tiled loops for free · PLDI 2007 |
Compilers and program optimization › loop optimization
loop tiling |
0.1 | 1 | 2012 | Parameterized loop tiling · ACM Trans. Program. Lang. Syst. 2012 |
Compilers and program optimization
loop transformation |
0.1 | 1 | 2007 | Multi-level tiling: M for the price of one · SC 2007 |
Compilers and program optimization › loop transformation
multi-level tiling |
0.1 | 1 | 2007 | Multi-level tiling: M for the price of one · SC 2007 |
Compilers and program optimization › loop transformation
register tiling |
0.1 | 1 | 2007 | Multi-level tiling: M for the price of one · SC 2007 |
Parallel and multicore computing › parallelization strategies
coarse-grained parallelism |
0.0 | 1 | 2012 | Parameterized loop tiling · ACM Trans. Program. Lang. Syst. 2012 |
Methods — techniques the papers use, named apart from their topics
symbolic fourier-motzkin elimination · 0.3polyhedral compilation · 0.3polyhedral code generation · 0.1parameterized tiling · 0.1symbolic fourier-motzkin · 0.1bounding box · 0.1auto-tuning · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2012 | Parameterized loop tilingabstractLoop tiling is a widely used program optimization that improves data locality and enables coarse-grained parallelism. Parameterized tiled loops, where the tile sizes remain symbolic parameters until runtime, are quite useful for iterative compilers and autotuners that produce highly optimized libraries and codes. Although it is easy to generate such loops for (hyper-) rectangular iteration spaces tiled with (hyper-) rectangular tiles, many important computations do not fall into this restricted domain. In the past, parameterized tiled code generation for the general case of convex iteration spaces being tiled by (hyper-) rectangular tiles has been solved with bounding box approaches or with sophisticated and expensive machinery. We present a novel formulation of the parameterized tiled loop generation problem using a polyhedral set called the outset . By reducing the problem of parameterized tiled code generation to that of generating standard loops and simple postprocessing of these loops, the outset method achieves a code generation efficiency that is comparable to existing code generation techniques, including those for fixed tile sizes. We compare the performance of our technique with several other tiled loop generation methods on kernels from BLAS3 and scientific computations. The simplicity of our solution makes it well suited for use in production compilers—in particular, the IBM XL compiler uses the inset-based technique introduced in this article for register tiling. We also provide a complete coverage of parameterized tiling of perfect loop nests by describing three related techniques: (i) a scheme for separating full and partial tiles; (ii) a scheme for generating tiled loops directly from the abstract syntax tree representation of loops; (iii) a formal characterization of parameterized loop tiling using bilinear forms and a Symbolic Fourier-Motzkin Elimination (SFME)-based parameterized tiled loop generation method. Lakshminarayanan Renganarayanan, DaeGon Kim, Michelle Mills Strout, Sanjay V. Rajopadhye |
ACM Trans. Program. Lang. Syst. | 2 |
| 2007 | Scheduling in the Z-Polyhedral ModelabstractThe polyhedral model is extensively used for analyses and transformations of regular loop programs, one of the most important being automatic parallelization. The model, however, is limited in expressivity and the need for the generalization to more general class of programs has been widely known. Analyses and transformations in the polyhedral model rely on certain closure properties. Recently, these closure properties were extended to programs where variables may be defined over unions of Z-polyhedra which are the intersection of polyhedra and lattices. We present the scheduling analysis for the automatic parallelization of programs in the Z-polyhedral model, and obtain multidimensional schedules through an ILP formulation that minimizes latency. The resultant schedule can then be used to construct a space-time transformation to obtain an equivalent program in the Z-polyhedral model. Gautam Gupta, DaeGon Kim, Sanjay V. Rajopadhye |
IPDPS | 2 |
| 2007 | Parameterized tiled loops for freeabstractParameterized tiled loops-where the tile sizes are not fixed at compile time, but remain symbolic parameters until later--are quite useful for iterative compilers and "auto-tuners" that produce highly optimized libraries and codes. Tile size parameterization could also enable optimizations such as register tiling to become dynamic optimizations. Although it is easy to generate such loops for (hyper) rectangular iteration spaces tiled with (hyper) rectangular tiles, many important computations do not fall into this restricted domain. Parameterized tile code generation for the general case of convex iteration spaces being tiled by (hyper) rectangular tiles has in the past been solved with bounding box approaches or symbolic Fourier Motzkin approaches. However, both approaches have less than ideal code generation efficiency and resulting code quality. We present the theoretical foundations, implementation, and experimental validation of a simple, unified technique for generating parameterized tiled code. Our code generation efficiency is comparable to all existing code generation techniques including those for fixed tile sizes, and the resulting code is as efficient as, if not more than, all previous techniques. Thus the technique provides parameterized tiled loops for free! Our "one-size-fits-all" solution, which is available as open source software can be adapted for use in production compilers. Lakshminarayanan Renganarayanan, DaeGon Kim, Sanjay V. Rajopadhye, Michelle Mills Strout |
PLDI | 2 |
| 2007 | Multi-level tiling: M for the price of oneabstractTiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. High-performance implementations use multiple levels of tiling to exploit the hierarchy of parallelism and cache/register locality. Efficient generation of multi-level tiled code is essential for effective use of multi-level tiling. Parameterized tiled code, where tile sizes are not fixed but left as symbolic parameters can enable several dynamic and run-time optimizations. Previous solutions to multi-level tiled loop generation are limited to the case where tile sizes are fixed at compile time. We present an algorithm that can generate multi-level parameterized tiled loops at the same cost as generating single-level tiled loops. The efficiency of our method is demonstrated on several benchmarks. We also present a method-useful in register tiling-for separating partial and full tiles at any arbitrary level of tiling. The code generator we have implemented is available as an open source tool. DaeGon Kim, Lakshminarayanan Renganarayanan, Dave Rostron, Sanjay V. Rajopadhye, Michelle Mills Strout |
SC | 1 |
| 2006 | An Improved Systolic Architecture for LU DecompositionabstractLU-Decomposition is a classic problem for which many systolic array implementations have been proposed, the best of which takes 3n-3 time on n2/2 PEs, for a dense, nxn matrix. In this paper, we first give a proof that if only nearest neighbor communication is allowed, this time is a lower bound. We then generalize it to 2n + n/k - 3 time if one allows k-bounded broadcasts (i.e., if it takes m/k time steps to broadcast a value to m destination nodes). We also present a new architecture with this improved execution time, which uses n2/2 PEs, each one consisting of two multiplier-subtractor units, but active only on alternate cycles. This leads to a speedup and efficiency of kn2/(6k+3) and 2k/(6k + 3) respectively. For k = 1, our proposed architecture achieves the performance of the best previously known systolic array implementation. Special cases of our results include similar improvements to algorithms for solving (upper and lower) triangular linear systems by (forward and backward) substitution. DaeGon Kim, Sanjay V. Rajopadhye |
ASAP | 1 |