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Zeyad Alkhalifa

dblp:76/5027 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1999
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 54% Electronic design automation · 46%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › hardware verification
assertion-based verification
0.011999
Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection · IEEE Trans. Parallel Distributed Syst. 1999
Hardware reliability and fault tolerance › error detection
control-flow error detection
0.011999
Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection · IEEE Trans. Parallel Distributed Syst. 1999
Electronic design automation › hardware verification and test
fault coverage
0.011999
Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection · IEEE Trans. Parallel Distributed Syst. 1999
Hardware reliability and fault tolerance
fault injection
0.011999
Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection · IEEE Trans. Parallel Distributed Syst. 1999
Hardware reliability and fault tolerance › error detection
on-line error detection
0.011999
Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection · IEEE Trans. Parallel Distributed Syst. 1999

Methods — techniques the papers use, named apart from their topics

fault injection · 0.0error injection · 0.0
YearPublicationVenuePosition
1999 Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection
abstract
This paper evaluates the concurrent error detection capabilities of system-level checks, using fault and error injection. The checks comprise application and system level mechanisms to detect control flow errors. We propose Enhanced Control-Flow Checking Using Assertions (ECCA). In ECCA, branch-free intervals (BFI) in a given high or intermediate level program are identified and the entry and exit points of the intervals are determined. BFls are then grouped into blocks, the size of which is determined through a performance/overhead analysis. The blocks are then fortified with preinserted assertions. For the high level ECCA, we describe an implementation of ECCA through a preprocessor that will automatically insert the necessary assertions into the program. Then, we describe the intermediate implementation possible through modifications made on gee to make it ECCA capable. The fault detection capabilities of the checks are evaluated both analytically and experimentally. Fault injection experiments are conducted using FERRARI to determine the fault coverage of the proposed techniques.
Zeyad Alkhalifa, Suku Nair, Narayanan Krishnamurthy, Jacob A. Abraham
IEEE Trans. Parallel Distributed Syst.1