In this paper, we present a new approach to model the impact of cross-coupling noise on interconnect delay. We introduce a new linear driver model that accurately models the noise pulse induced on a switching signal net due to cross coupling capacitance. The proposed model effectively captures the non-linear behavior of the victim driver gate during the transition and has an average error below 8% whereas the traditional approach using a Thevenin model incurs an average error of 48%. We also discuss the worst case alignment of the aggressor net transitions with respect to the victim net transition, emphasizing the need to maximize not merely the delay of the interconnect alone but the combined delay of the interconnect and receiver gate. We show that the worst case alignment of an aggressor net transition is a function of the receiver gate output loading, victim transition edge rate, and the noise pulse width and height and hence propose a pre-characterization approach to efficiently predict the worst-case alignment. The proposed methods were implemented in an industrial noise analysis tool called ClariNet. Results on industrial designs are presented to demonstrate the effectiveness of our approach.

Conceptual design, the preliminary phase of design in which both well-defined problem specifications and high level design solutions are developed, is becoming increasingly important as design complexity increases. In spite of the importance of this activity, few tools exist to support this phase of design. In this paper we present a systematic and flexible model of conceptual design and describe how this model has been employed to realize a prototype conceptual design process management environment, called Clio II.

We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits.To overcome the complexity of state dependence in average leakage estimation, we introduce the concept of "dominant leakage states" and use state probabilities.Our method achieves speed-ups of 3 to 4 orders of magnitude over exhaustive SPICE simulations while maintaining accuracies within 9% of SPICE.This accurate estimation is used in a new sensitivity-based leakage and performance optimization approach for circuits using dual V t processes.In tests on a variety of industrial circuits, this approach was able to obtain 81-100% of the performance achievable with all low V t transistors, but with 1/3 to 1/6 the stand-by current.