This paper proposes a virtual cluster architecture, which executes multi-cluster VLIW programs with a reduced number of clusters in a time-sharing fashion. The interleaved sub-VLIWs help to hide instruction latencies significantly, and thus the proposed virtual cluster will have advantages of (1) reduced forwarding complexity in the processor datapath, (2) improved programming model for further code optimizations, and (3) supporting composite instructions without any extra functional unit. In our experiments with a 4-cluster VLIW DSP, the 28 forwarding paths inside a cluster are completely eliminated, which contributes to savings of 21.71% delay and 17.56% silicon area. Moreover, the virtual cluster has been verified to have better efficiency on its code sizes and execution times for its improved programming model for various DSP kernels.

This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-centric instruction set and a corresponding latency-insensitive micro-architecture, where the hardware design is optimized concurrently with its automatic software generator. The proposed DSP core has 3/spl times/ performance (in cycles) of those found in commercial dual-core application processors with similar computing resources. The silicon implementation in UMC 0.18/spl mu/m 1P6M CMOS technology operates at 314MHz and consumes only 52mW average power.

This paper provides an overview of the parallel architecture core (PAC) project led by SoC Technology Center of Industrial Technology Research Institute (STC/ITRI) in Taiwan. The background of PAC project, a brief introduction to PAC core technologies, PAC SoC development suite, PAC benchmarks, and applications are presented. The main objective of the PAC development plan is to enhance industrial development competitiveness in the core technology related to key components, especially for portable multimedia applications

This paper presents a programmable FIR core with a compact adder-based computing engine and an automatic code generator. The FIR core saves 50% area of conventional MAC-based cores in the 0.13/spl mu/m implementation. Besides, the complexity-aware code generator synthesizes optimized FIR programs for a user-defined sampling period. It explores an optimal scaling factor with common subexpression elimination automatically. In our simulations, the proposed approach reduces about 10% /spl sim/ 18% computing time of MAC-based FIR cores with comparable filtering performance.

This paper presents a unified processor core with two operation modes. The processor core works as a compiler-friendly MIPS-like core in the RISC mode, and it is a 4-way VLIW in its DSP mode, which has distributed and ping-pong register organization optimized for stream processing. To minimize hardware, the DSP mode has no control construct for program flow, while the data manipulation RISC instructions are executed in the DSP datapath. Moreover, the two operation modes can be changed instruction by instruction within a single program stream via the hierarchical instruction encoding, which also helps to reduce the VLIW code sizes significantly. The processor has been implemented in the UMC 0.18um CMOS technology, and its core size is 3.23mmx3.23mm including the 32KB on-chip memory. It can operate at 208MHz while consuming 380.6mW average power.

As the VLSI technology advances continuously, ASIC can easily achieve the required performance and most of them are actually over-designed. Thus, architecture shrinking is inevitable in optimal designs especially when supply voltages are getting lower. However, conventional designs starting from minimization of algorithmic operations (e.g. multiply) may not always lead to optimal architectures, for the wires and the interconnection complexity significantly grow and have become predominant. This paper explores algorithms and architectures for the 2-D transform in H.264/AVC, of which the operations are very simple (i.e. only shift and add). We have shown that fewer operations do not always result in more compact designs. In our experiments with the UMC 0.18 /spl mu/m CMOS technology, the most straightforward matrix multiplication without separable 2-D operation or any fast algorithm has the best area efficiency for DI-size (720/spl times/480) video at 30 fps. It saves 48%, 34%, and 16% silicon area of the previous works respectively.

This paper presents a memory-efficient approach to realize the cyclic convolution and its application to the discrete cosine transform (DCT). We adopt the way of distributed arithmetic (DA) computation, exploit the symmetry property of DCT coefficients to merge the elements in the matrix of DCT kernel, separate the kernel to be two perfect cyclic forms, and partition the content of ROM into groups to facilitate an efficient realization of a one-dimensional (1-D) N-point DCT kernel using (N-1)/2 adders or subtractors, one small ROM module, a barrel shifter, and ((N-1)/2)+1 accumulators. The proposed memory-efficient design technique is characterized by rearranging the content of the ROM using the conventional DA approach into several groups such that all the elements in a group can be accessed simultaneously in accumulating all the DCT outputs for increasing the ROM utilization. Considering an example using 16-bit coefficients, the proposed design can save more than 57% of the delay-area product, as compare with the existing DA-based designs in the case of the 1-D seven-point DCT. Finally, a 1-D DCT chip was implemented to illustrate the efficiency associated with the proposed approach.

MPEG-4 shape coding comprises context-based arithmetic encoding (CAE) as its centerpiece. Since the CAE algorithm has a complicated coding procedure and strong data dependency, it is hard to exploit its pipeline and parallel facilities. Furthermore, to encode multiple symbols within one clock cycle, it needs to overcome the issues of extracting multiple contexts of these symbols, deriving multiple probabilities from these contexts, and performing multiple multiplicative range update operations. This paper presents an efficient pipelined multisymbol CAE architecture for real-time MPEG-4 shape encoding. The proposed design is based on the inherent characteristics of binary alpha blocks as well as the numerical properties of the probabilities indexed by the contexts, and it is capable of encoding either a singe symbol or multiple symbols within each clock cycle. To overcome the aforementioned issues under the consideration of the hardware cost and the critical path delay, only symbols with a particular set of contexts are chosen to be processed simultaneously within the same clock cycle. Theoretical analysis shows that the majority of symbols have contexts belonging to this particular set, and therefore CAE processing can be significantly accelerated. An example VLSI implementation of proposed architecture that encodes two symbols within each clock cycle without sacrificing the clock rate can achieve a speedup of 1.47 in comparison with traditional CAE architectures. This particular two-symbol design can support MPEG-4 Main Profile at levels 3 and 4 under extreme and typical conditions, respectively. When synthesized from Verilog RTL design by using TSMC 0.35-/spl mu/m 1P4M CMOS technology, the design can run at 90 MHz.

The ongoing advancements in VLSI technology allow system-on-a-chip (SoC) design to integrate heterogeneous control and computing functions into a single chip. On the other hand, the pressures of area and cost lead to the requirement for a single, shared off-chip DRAM memory subsystem. To satisfy different memory access requirements for latency and bandwidth of these heterogeneous functions to this kind of DRAM memory subsystem, a quality-aware memory controller is important. This paper presents an efficient multilayer, quality-aware memory controller that contains well-partitioned functionality layers to achieve high DRAM utilization while still meet different requirements for bandwidth and latency. Layer 0, also called memory interface socket, is a configurable, programmable, and high-efficient SDRAM controller for designers to rapidly integrate SDRAM subsystem into their designs. Together with Layer 1 quality-aware scheduler, the memory controller also has the capability to provide quality-of-service guarantees including minimum access latencies and fine-grained bandwidth allocation for heterogeneous control and computing functional units in SoC designs. Moreover, Layer 2 built-in address generator designed for multimedia processing units can effectively reduce the address bus traffic and therefore further increase the efficiency of on-chip communication. Experimental results of a digital set-top-box emulation system show that the access latency of the latency-sensitive data flows can be effectively reduced by 37%-65% and the memory bandwidths can be precisely allocated to bandwidth-sensitive data flows with a high degree of control.

The multimedia SoC usually integrates programmable digital signal processors (DSP) to accelerate data-intensive computations. But the DSP and the host processor (e.g. ARM) are both designed for standalone uses, and they must have overlapped functionalities and thus some redundant components. In this paper, we propose a compact DSP core for dual-core multimedia SoC and its complete software development tools. The DSP core contains a dataflow engine that is composed of off-the-shelf memory modules with limited ports, and we have investigated software techniques extensively to reduce the hardware complexity as the principles of VLIW processors. Moreover, the DSP is equipped with novel static floating-point units to emulate expensive floating-point DSP operations at low cost. In our experiments, this core has about thrice the performance (estimated in execution cycles) of Analog Devices ADSP-218x with similar computing resources. Our first prototype in the 0.35um CMOS technology operates at 100MHz and consumes 122mW power. The core size is 2.8mm2 including an embedded DMA controller and the AMBA AHB interface.

The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for high-performance real-time DSP applications. But the two major weaknesses in VLIW processors prevent the integration of more functional units (FU)for a higher instruction issuing rate & the dramatically growing complexity in the register file (RF), and the poor code density. We propose a novel ring-structure RF, which partitions the centralized RF into 2N subblocks with an explicit N-by-N switch network for N FU. Each subblock only requires access ports for a single FU. We also propose the hierarchical VLIW encoding with variable-length RISC-like instructions and NOP removal. The ring-structure RF saves 91.88% silicon area and reduces 77.35% access time of the centralized RF. Our simulation results show that the proposed instruction set architecture with the exposed ring-structure RF has comparable performance with the state-of-the-art DSP processors. Moreover, the hierarchical VLIW encoding can save 32%/spl sim/50% code sizes.

As the concurrent functional units in media processors increase continuously to meet the performance needs, the required access (i.e. read or write) ports of the centralized register file (RF) multiply rapidly and cannot be efficiently implemented. We propose a novel ring-structure RF, which is composed of register sub-blocks identical to the RF for a single functional unit. Data exchanges among functional units occur on the switch network of the ring registers. The proposed RF has been integrated into a four-way VLIW DSP processor successfully that demonstrates its effectiveness in DSP kernels. The synthesis result shows that our proposed ring-structure RF saves 91.88% silicon area of the centralized one, while reducing its access time by 77.35%.

This paper presents the systematic synthesis of multiplier-less FIR filters with a novel complexity-aware quantization algorithm. Both signed-digit representations and common subexpression elimination (CSE) are investigated to reduce the computational complexity at the bit level. For comparable filter responses, the simulation shows that our approach requires only half (49.06%/spl sim/ 50.94%) additions of the straightforward quantized filters. Both with CSE, our FIR synthesizer has comparable results with the CSD-encoded coefficients, which have the theoretically minimum non-zero terms. Moreover, our approach outperforms CSD in most cases because of the direct control over additions and the zero-overhead insertion of non-zero terms.

This paper presents a generalized earliest-first (GEF) addition algorithm to accelerate carry propagation addition (CPA). A set of operators and notations have been developed to describe and analyze traditional carry-lookahead or conditional-sum-based algorithms. The proposed GEF algorithm schedules bit-level operations of CPA in an earliest-first manner to reduce the overall latency. With the aid of the developed operators and notations, the algorithm can be generalized to any algorithm based on carry-lookahead or conditional-sum rule. An adder generated by using the GEF algorithm outperforms traditional algorithms when inputs do not arrive simultaneously.

This work explores the data reuse properties of full-search block-matching (FSBM) for motion estimation (ME) and associated architecture designs, as well as memory bandwidth requirements. Memory bandwidth in high-quality video is a major bottleneck to designing an implementable architecture because of large frame size and search range. First, the memory bandwidth in ME is analyzed and the problem is solved by exploring data reuse. Four levels are defined according to the degree of data reuse for previous frame access. With the highest level of data reuse, one-access for frame pixels is achieved. A scheduling strategy is also applied to data reuse of the ME architecture designs and a seven-type classification system is developed that can accommodate most published ME architectures. This classification can simplify the work of designers in designing more cost-effective ME architectures, while simultaneously minimizing memory bandwidth. Finally, a FSBM architecture suitable for high quality HDTV video with a minimum memory bandwidth feature is proposed. Our architecture is able to achieve 100% hardware efficiency while preserving minimum I/O pin count, low local memory size, and bandwidth.

Real-time three-dimensional (3D) graphics is emerging rapidly in multimedia applications, but it suffers from requirements for huge computation, high bandwidth, and large buffer. In order to achieve hardware efficiency for 3D graphics rendering, we propose a novel approach named index rendering. The basic concept of index rendering is to realize a 3D rendering pipeline by using asynchronous multi-dataflows. Triangle information can be divided into several parts with each part capable of being transferred independently and asynchronously. Finally, all data are converged by the index to generate the final image. The index rendering approach can eliminate unnecessary operations in the traditional 3D graphics pipeline, the unnecessary operations are caused by the invisible pixels and triangles in the 3D scene. Previous work, deferred shading, eliminates the operations relating to invisible pixels, but it requires huge tradeoffs in bandwidth and buffer size. With index rendering, we can eliminate operations on both invisible pixels and triangles with fewer tradeoffs as compared with the deferred shading approach. The simulation and analysis results show that the index rendering approach can reduce 10%-70% of lighting operations when using the flat and Gouraud shading process and decrease 30%-95% when using Phong shading. Furthermore, it saves 70% of buffer size and 50%-70% of bandwidth compared with the deferred shading approach. The result also indicates that this approach of index rendering is especially suitable for low-cost portable rendering devices. Hence, index rendering is a hardware-efficient architecture for 3D graphics, and it makes rendering hardware more easily integrated into multimedia systems, especially system-on-a-chip (SOC) designs.

Subdivision algorithms have been extensively used in computer graphics to produce a more accurate geometry model. For the purpose of integration into the context of a standard graphics pipeline for real-time display, we can only make use of the available information of one triangle. We propose a low computation cost algorithm to subdivide a polygon using vertex coordinates and vertex normal vectors of one triangle. Compared with other suitable algorithms, our algorithm produces decent results with lowest computational complexity. We also consider the generation of interpolated normal vectors and texture mapping parameters. Detailed comparisons among other suitable algorithms are presented.

In this paper, we present a carry-save to signed-digit (CS2SD) recoder with high performance and small area. The recoder can be employed in common fused addition-multiplication operation which is widely used in various signal-processing applications. Our design shows 18% area-time product improvement over the traditional designs.

With the advent of the World Wide Web and the services on it, there is a strong demand for the nodes that make Internet routing with guaranteed speed and throughput. Current 40-channel WDM (Wavelength Division Multiplexing) has boosted a single 2.5 Gbps OC-48 link to 100 Gbps, so the requirement to make IPv4 (Internet Protocol version 4) routing table lookup is 100 MLPS (million lookups per second.) The emerging 96-channel WDM and 10 Gbps OC-192 fibers certainly demand much more. Previous works on fast IPv4 routing table lookup used indirect RAM indexing to CPU caching or CAM (Content Addressable Memory) to achieve a few or tens MLPS. Their theoretical best performances depend on the memory access speed and some of them are not extensible to accommodate the forthcoming IPv6. In this paper we describe a novel way to do this work with only a FPGA, and this approach, which utilizes the logic modeling and minimization techniques, promises a capability to make IPv4 and (IPv6) routing decisions in a pipelined fashion within only a FPGA CLB delay time.

Real-time 3-D graphics emerges rapidly in multimedia applications, but suffers from huge computation requirement. In 3-D graphics, lighting is an essential operation, but requires high computation power. In fact, many lighting calculations are redundant due to invisible polygons. To explore computation efficiency, we propose a novel deferred lighting approach. This approach defers lighting calculation after visibility comparison, hence eliminates lighting calculation on invisible polygon. Simulation result shows that deferred lighting approach can save 22%-58% of lighting calculation in flat shading and Gouraud shading, and initial cost of Taylor series in fast Phong shading.

This paper proposes a class of motion estimation operation technologies and MSD-first comparators, which are implemented using on-line arithmetic. In on-line arithmetic, the numbers are represented in the redundant binary representation, where carry/borrow propagation chains are eliminated. This is because most significant digit (MSD) first accumulates and subtraction algorithms are applied by signed-digit (SD) representations. Most of previous MSD-first researches are used to decrease the initiation interval of recursive computations, particularly in IIR filters. In motion picture compression process, motion estimation (ME) represents a heavy loading. Intact motion estimation implementation using on-line arithmetic adopts MSD-first operations. This benefits reducing redundant calculation in two parts: 1. delete redundant summation of absolute different (SAD) calculation if existence another smaller SAD has been ascertained. 2. Decrease redundant lower-digits calculation if motion vector has been found. We developed two keys for the MSD-first algorithm to implement ME, including SAD calculation and SD comparison. This MSD-first ME algorithm can also cooperate with existent search algorithms to lower SAD computation further. This MSD-first ME algorithm can reduce 55% primitive SD operations.

This paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we propose a new modified Booth encoding (MBE) scheme to improve the performance of traditional MBE schemes. For final addition, a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA). The proposed algorithm can optimize final adder according to the given cell properties and input delay profile. Compared with a binary tree-based conditional-sum adder, the speed performance improvement is up to 25 percent. On average, the design developed herein reduces the total delay by 8 percent for parallel multiplier. The whole design has been verified by gate level simulation.

This paper presents a cost-effective processor core design that features the simplest hardware and is suitable for discrete cosine transform/indiscrete cosine transform (DCT/IDCT) operations in H.263 and digital camera. This design combines the techniques of fast direct two-dimensional DCT algorithm, the bit level adder-based distributed arithmetic, and common subexpression sharing to reduce the hardware cost and enhance the computing speed. The resulting architecture is very simple and regular such that it can be easily scaled for higher throughput rate requirements. The DCT design has been implemented by 0.6 /spl mu/m SPDM CMOS technology and only costs 1493 gate count, or 0.78 mm/sup 2/. The proposed design can meet real-time DCT/IDCT requirements of the H.263 codec system for QCIF image frame size at 10 frames/s with 4:2:0 color format. Moreover, the proposed design still possesses additional computing power for other operations when operating at 33 MHz.

In this paper an architecture of full-search block matching motion estimation suitable for high quality video is proposed. Minimum memory bandwidth is an important requirement in motion estimation architecture especially when dealing with high quality video such as large frame size video. Memory bandwidth will increase to an unrealistically high value without careful consideration, which no cost efficient solution can afford. This architecture is designed for overcoming the frame memory bandwidth bottleneck by exploiting the maximum data reuse property. This is done by setting up local memory for storing frame data. The size of local memory is also optimized to near minimum value, only a little overhead is introduced. Due to the reduction of memory bandwidth, the costs of the frame memory modules, I/O pin count and the power consumption can be reduced but 100% hardware efficiency is still achieved. Simple and regular interconnections are featured to ensure high speed operation by an efficient and distributed local memory organization.

Most FIR filter realizations use the inputs and coefficients directly to compute the convolution. We present a low power and high speed FIR filter designs by using first order difference between inputs and various orders of differences between coefficients. This design first reformulates the FIR operations with the differences in the algorithm level. Then, in the architecture level, we adopt the distributed arithmetic (DA) architecture to exploit the probability distribution such that the power consumption can be reduced further. The design is applied to an example FIR filter to quantify the energy savings and speedup. It shows lower power consumption than the previous design with the comparable performance.

The video signal processor (VSP) is very suitable for various video standards and provides high flexibility for system development. To offer high throughput and hardware efficiency, we propose a concurrent VSP architecture. Our VSP contains three vector function units that work in parallel. The vector function units adopt a vector-pipeline architecture to increase the throughput and reduce the clock cycle time. To take full advantage of the parallel function units, we design a concurrent control unit which eliminates hazards and schedules instructions. The control unit uses the techniques of reservation stations, renaming buffer, out-of-order execution and in-order completion. With these design considerations, our VSP can encode the full-CIF H.261 video with 30 frames/s at an operation frequency of 47 MHz in the Verilog simulation. We have mapped the design on Xilinx FPGA devices and verified it in a logic analyzer.

Block matching is a widely used motion estimation algorithm in current video systems. Among typical searching strategies, the full search scheme provides better precision and regular data flow as well as higher parallelism, a characteristic that is advantageous for VLSI implementation. However, the huge computation load incurred by full search results in high cost, especially in high pixel rate applications. Since the block matching algorithm is used in a wide range of pixel rates, an architecture that is cascadable and offers variable computing power is promising. An approach based on dependence graph (DG) is proposed to analyze the operation sequence and data flow of full search block matching. The approach employs a transformation on DGs, called slice and tile, to produce different forms of DGs. Through this technique, most existing architectures can be represented in graphs for analysis, and new architectures can be found. A new architecture is presented that features cascadable modules of processing elements (PEs) with simple interconnection. Therefore, flexibility in computing power is available. The other advantages include variable sizes of the search area and 100% PE utilization. These characteristics offer great flexibility and efficiency for different applications. This architecture is implemented with thirty-two PEs in one chip that consists of 102 K transistors.>

This paper presents a novel VLSI array design for the 1-D discrete Hartley transform (DHT). Using the similar idea to the Chirp-Z transform, we develop an algorithm which can formulate the 1-D any-length DHT as cyclic convolutions. This algorithm owns higher flexibility in the transform length as compared with the existing approach of Guo, Liu, and Jen (see Proc. IEEE International Conference on Acoustics; Speech, and Signal Processing, p.v.621-v.624, 1992 and IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol.30, p.723-733, Oct. 1992). Moreover, we use the memory-based approach to realize the cyclic convolutions by systolic arrays and implement the multiplications by small ROMs and adders. The presented array not only outperforms the distributed arithmetic (DA) architectures in the hardware area, but also owns low input/output (I/O) cost, power dissipation, high computing speeds and flexibility in transform length.>

In this paper, a general memory-based approach to design VLSI arrays for the multi-dimensional (M-D) discrete Hartley transform (DHT) with any length is proposed. There are four parts of this approach: (1) a new M-D DHT formulation, (2) cyclic convolution representation, (3) systolic array realization, and (4) memory-based implementation. Deriving a new M-D DHT formulation avoids the undesirable overhead required in formal designs. Taking cyclic convolution provides high computing parallelism and low computation complexity. Using systolic array realisation results in high computing speeds and low I/O cost. Adopting the memory-based implementation yields low hardware cost and low power dissipation. In summary the proposed approach will lead to efficient and high-performance VLSI array designs for the M-D DHT.>

A new design and implementation approach for the discrete Fourier transform (DFT) and discrete cosine transform (DCT) is discussed. The approach, called memory-based approach, is based on a design concept of combining and exploiting both the advantages induced from the systolic array architectures and the efficient implementation techniques of substituting multipliers by read-only-memory (ROM) together. Based on this approach, the proposed arrays feature high computing speeds, low complexity and hardware cost of the processing elements (PEs), and low I/O cost. Moreover, high regularity both among and inside the PEs can be found in the proposed arrays. These merits make the proposed designs much more feasible for VLSI implementation.>

High-performance implementations of recursive filters are discussed. They have both the higher speed and lower cost than conventional designs. The look-ahead scheme is applied and the relation between it and the array structure is derived which makes the highest speed available. Two-level pipelined systolic arrays are dedicated and proposed for such designs. They can reach the maximum throughput rate for both clustered and scattered look-ahead. In addition, to prevent the large overhead induced in the conventional two-stage synthesis for look-ahead transfer functions, a new approach from specification to final result directly is also presented. Due to the lack of any transformation, the hardware is less complex and the performance is improved significantly. Simulation results show the improvement attained is at least 10 dB.>

An algebraic representation is proposed for regular iterative algorithms that can be described as bundles of data flows with different wavefronts. A form corresponding to a geometric representation such as a dependence graph is obtained by modeling data flows with a generating function of a power series. The main attributes of systolic algorithms and arrays are revealed by a unique dataflow representation. This provides the ability to pipeline two or more systolic arrays solving different subproblems without intermediate buffering. An example is given to show a case in which the technique can be used.>

A package, named VLSI array architectures synthesizer (VAAS), to synthesize VLSI array architectures for DSP applications is presented. VAAS has been imbedded with the systematical synthesis method for systolic arrays, two-level pipelined systolic arrays, and multiple-array architectures. It provides a design environment with an algorithm description language, 3D graphical representations, performance evaluation, array simulation, a library of systolic algorithms, etc. Based on the environment, feasible VLSI array architectures for a DSP application can be exploited quickly. Two design examples are used to demonstrate the package.>

Autoregressive (AR) spectral estimation is widely used in various fields. However, a trade-off between performance and computational complexity is sometimes faced. Two recursive computing algorithms individually applied to the wide-sense stationary and highly nonstationary environments are presented. These algorithms have good numerical properties, high computing parallelism, and data locality. VLSI arrays are designed to realize the algorithms. The algorithms and arrays provide the potential of attaining high processing speed and good performance in real-time applications.>

A computationally efficient adaptive algorithm for the IBDA (innovations-based detection algorithm) is devised and realized with a systolic array so that is possesses both fast adaptation and good steady-state performance. The algorithm has superior numerical properties and computational complexity. It possesses high computing parallelism and good data locality, which are preferable in VLSI arrays. One systolic array example designed for the algorithm has an iteration time of (2N+1) and ((n/sup 2/+3n)/2) processing elements, where n is the number of states.>

The authors consider two implementation techniques for building a high-performance image-resampler VLSI chip. First, a two-level pipelined systolic array is designed for image resampling to give high parallelism in computation and high feasibility for VLSI implementation. Second, a modified two-pass resampling scheme is used to decrease the amount of required storage and increase the concurrency between two resampling passes. With the two techniques, the system can provide a throughput of one pixel in a clock period smaller than that for an adder.>