Integrated circuits have evolved to a stage where interconnections significantly limit their performance and functional complexity. We introduce a set of tools to perform highly accurate three-dimensional capacitance and resistance/thermal calculations of interconnect structures. We automatically generate these structures from layout information and a given process description. The main enhancement of our work is that we extract the interconnect characteristics after a complete and accurate topography simulation with previous optional lithography analysis, instead of elementary geometric blocks derived from simple analytical models. The capacitance and resistance/thermal extractor simulators are based on optimized finite-element methods, and the topography simulators use a cellular data-based approach.