The paper introduces the parallel version of the Light Speed Labeling (LSL) and compares it with the parallel versions of the competitors. A benchmark shows that the parallel Light Speed Labeling is ×1.8 faster than all the other algorithms for random images on average. This factor reaches ×3.2 for structured random images. More importantly, we show that thanks to its run-based processing (segments), LSL is intrinsically more efficient than all pixel-based algorithms.

Future embedded systems will have to support multiple and concurrent dynamic compute-intensive applications. These variable workloads can be handled by an efficient asymmetric MPSoC architecture, which integrates multithreaded processors as key processing elements. In this paper, we consider an asymmetric MPSoC architecture with a centralized controller and multiple multithreaded processors, which we call A-CMT (Asymmetric Chip Multi Threading). The centralized controller can implement 2 main types of thread scheduler architectures: VSMP (Virtual Symmetric Multi Processing), and SMTC (Symmetric Multi-Thread-Context). Each type can have a static or dynamic allocation. We show that static scheduling for the A-CMT with dynamic applications (such as connected component labeling) can become a bottleneck for the overall architecture's performance, which leverages the use of dynamic scheduling for VSMP and SMTC. The dynamic SMTC gave a maximum of 51% and 11% speedup compared to the static SMTC and dynamic VSMP respectively.

Biological Sequence Comparison is an important operation in Bioinformatics that is often used to relate organisms. Smith and Waterman proposed an exact algorithm (SW) that compares two sequences in quadratic time and space. Due to high computing and memory requirements, SW is usually executed on HPC platforms such as multicore clusters and CellBEs. Since HPC architectures exhibit very different hardware characteristics, porting an application between them is an error-prone time-consuming task. BSP++ is an implementation of BSP that aims to reduce the effort to write parallel code. In this paper, we propose and evaluate a parallel BSP++ strategy to execute SW in multiple platforms like MPI, OpenMP, MPI/OpenMP, CellBE and MPI/CellBE. The results obtained with real DNA sequences show that the performance of our versions is comparable to the ones in the literature, evidencing the appropriateness and flexibility of our approach.

As the fabrication technology node shrinks down to 90nm or below, high standby power becomes one of the major critical issues for CMOS high-speed computing circuits (e.g. logic and cache memory) due to the high leakage currents. A number of non-volatile storage technologies such as FeRAM, MRAM, PCRAM and RRAM and so on, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy 3D integration after CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and discuss their potential applications in the future from both the physics and architecture points of view.

With the increase in the design complexity of MP-SoC architectures, flexible and accurate processor simulators became a necessity for exploring the vast design space solutions. In this paper, we present a flexible cycle-accurate ISS model based on ArchC 2.0 language. The model can have a variable pipeline depth and can be integrated easily in any SoC design based on SystemC. Its performance and capabilities are demonstrated by running MiBench embedded benchmark suite, while extracting pipeline statistics for each application.

Efficiently using the hardware capabilities of the Cell processor, a heterogeneous chip multiprocessor that uses several levels of parallelism to deliver high performance, and being able to reuse legacy code are real challenges for application developers. We propose to use Generative Programming and more precisely template meta-programming to design an domain specific embedded language using algorithmic skeletons to generate applications based on a high-level mapping description. The method is easy to use by developers and delivers performance close to the performance of optimized hand-written code, as shown on various benchmarks ranging from simple BLAS kernels to image processing applications.

We consider the implementation of 16-bit floating point instructions on a Pentium 4 and a PowerPC G5 for image and media processing. By measuring the execution time of benchmarks with these new simulated instructions, we show that significant speed-up is obtained compared to 32-bit FP versions. For image processing, the speed-up both comes from doubling the number of operations per SIMD instruction and the better cache behavior with byte storage. For data stream processing with arrays of structures, the speed-up mainly comes from the wider SIMD instructions.

By examining the speed-up resulting from using Pentium 4 SIMD instructions for DSP kernels (FFT) and two different multimedia programs (the MPEG-2 codec and a matching pursuit video codec), we discuss the hardware and software issues that limit performance. The cost of unaligned memory accesses and the lack of instructions summing the different parts of an XMM register in the present implementation of Intel SIMD instructions limit the efficiency of dot products. C programmer's habits often prevent compiler vectorization or complicate in-lining of assembly code in many DSP and multimedia applications.

Multiprocessors and high performance networks allow building CLUsters of MultiProcessors (CLUMPs). One distinctive feature over traditional parallel computers is their hybrid memory model (message passing between the nodes and shared memory inside the nodes). We evaluate the performance of a cluster of dual processor PCs connected by a Myrinet network for NAS benchmarks using two programming models: a Single Memory Model based on the MPICH-PM/CLUMP library of the RWCP and a Hybrid Memory Model using MPICH-PM and OpenMP. MPI programs are used as the reference in all experiments involving programming models. We compare dual processor node configurations speedup versus uniprocessor node configurations for each model. We demonstrate that the superiority of one model over the other depends on the features of the applications. In particular, we detail the speedup results from breakdowns of the benchmark execution times and from measurements of hardware counters.

The hybrid memory model of clusters of multiprocessors raises two issues: programming model and performance. Many parallel programs have been written by using the MPI standard. To evaluate the pertinence of hybrid models for existing MPI codes, we compare a unified model (MPI) and a hybrid one (OpenMP fine grain parallelization after profiling) for the NAS 2.3 benchmarks on two IBM SP systems. The superiority of one model depends on 1) the level of shared memory model parallelization, 2) the communication patterns and 3) the memory access patterns. The relative speeds of the main architecture components (CPU, memory, and network) are of tremendous importance for selecting one model. With the used hybrid model, our results show that a unified MPI approach is better for most of the benchmarks. The hybrid approach becomes better only when fast processors make the communication performance significant and the level of parallelization is sufficient.

Algorithms for the sum of two (three and four) digits in the binary stored-carry number system, using the smallest set of values for the positional sum, are presented. The corresponding adders, which use multivalued current-mode circuits, are also presented. The implementation of multioperand additions using these adders is compared with the usual binary implementation.>

Mismatches between on-chip high performance CPU and data access times is the basic reason for the increasing gap between peak and sustained performance in distributed memory parallel computers. We propose the concept of balanced architectures, based on a network with a dynamic topology and communication patterns determined at compile time. The corresponding processing element is a cacheless CPU, which can achieve a 1 FLOP/clock cycle rate. Network and PE features are presented. An example shows that balanced architectures keep efficiency when scaling.

The authors present RAPID a highly parallel processor which includes an extended relational algebra and text retrieval capacities in its instruction set. RAPID operates in parallel with the transfer of relevant data on the host machine bus, in a null apparent time. It is implemented with several copies of a specialized component using RISC (reduced-instruction-set-computer)-like technology, though its instructions are very high-level ones. It fully uses the resources of HCMOS3 technology and of full-custom design. A first version of the processor is presently being implemented.>

We present a TSC multivalued I2L comparator which uses multivalued current inputs and two binary voltage outputs. This circuit is self-testing and fault-secure for single faults (either "stuck-at" or "skew" faults). It is the basic circuit to realize TSC checkers for nonseparable or separable codes. The schemes are simpler than the designs of the TSC combinational checkers.

A general method for implementing ternary circuits with binary integrated circuits is described. The conditions are given for a particular technology to be able to implement ternary circuits. For TTL, COSMOS, and ECL technologies, the necessary circuits are developed. Formulas are provided to obtain the minimum circuit according to the particular function required. Simplification rules corresponding to each technology are given. Some examples illustrate the method. Some dynamical characteristics are shown. Extensions of these results to other technologies and to n-valued circuits are possible.