This paper presents a bioinspired, multi-channel auditory signal encoder based on volatile memristors, designed to mimic the short-term adaptation behavior of the human auditory system. The system integrates a threshold generator with an asynchronous delta modulator (ADM) to dynamically adjust threshold voltages based on real-time memristor behavior. The encoder is implemented with standard 130nm CMOS technology, occupying a compact area of 0.44 mm × 0.185 mm per channel and consuming 299.85 μW per channel. The adaptive resolution of the encoder is validated in simulations using a memristor model derived from real device data, demonstrating adaptive output firing rates as a result of memristor resistance volatility. With a maximum delay of 45.25 ns for a 1 kHz sound input, the design is well-suited for spike-domain neuromorphic systems.

The memristor, as a cutting-edge nanodevice, has been studied for decades and gives rise to a wide range of applications across various fields. Although small signal analysis are crucial in circuit design and memristors exhibit unique Alternating Current (AC) features such as memimpedance, extensive research and reliable AC models are still lacking. This paper presents a memristor small-signal AC model that captures memimpedance effect by statistical modelling the complex impedance as a function of stimulus frequency and resistive state (RS). The model has been developed in Verilog-A and verified in Cadence Virtuoso Electronic Design Automation (EDA) tools. The proposed model can support small-signal analysis for hybrid CMOS/memristor circuits and systems, providing more realistic memristor AC behaviours. The modelled memimpedance signature is expected to enable more emerging circuit applications.

The development of non-volatile Compute-In-Memory (nvCIM) technology has demonstrated significant potential in addressing the data movement and Multiply-and-Accumulate (MAC) bottlenecks in machine learning algorithms by enabling parallel analog Vector-Matrix Multiplication (VMM) operations directly within memory arrays. In this work, we introduce SPIKA, a fully integrated RRAM-CMOS chip designed for neural network acceleration. The key innovation of SPIKA lies in its ability to efficiently transfer input signals to output signals with minimal circuit overhead. The VMM operation is performed in the time domain, with the dot product accumulated on a switched capacitor, eliminating the need for high-resolution, power-intensive data converters. Implemented using commercially available 180nm technology, SPIKA operates on a 64×128 crossbar and utilizes 4-bit inputs, ternary weights, and 5-bit outputs. The chip is evaluated on the MNIST dataset, achieving a peak throughput of 1092 GOPS and an energy efficiency of 195 TOPS/W.

Photoplethysmography (PPG) has been widely used in consumer and medical devices for assessing heart rate blood oxygen and blood pressure levels, together with electrocardiography (ECG). One of the major challenges is recording PPG with fast changing ambient light and motion artefacts that generating a changing baseline of the signal. Light to digital converters (LDCs) proposed in recent years show excellent resolution and power efficiency, however it may get saturated during fast ambient and motion events. Existing chopping ambient light removal and hysteresis DC removal techniques cannot track fast-changing components. Therefore, this paper proposes a current domain level crossing-based technique to assist a dual slope LDC, including a dynamic biased low-power continuous time comparator. The PPG readout frontend is implemented in a 55nm standard CMOS process and consumes 12.4μW-56.6μW depending on the ambient light intensity. It achieves a dynamic range of 102dB and an SNDR of 75dB at AC signal path.

This paper proposes a Vref-compensated memristor-assisted CDAC background calibration scheme for Nyquist SAR ADCs. The proposed CDAC is implemented in a 12-bit 5 MS/s asynchronous SAR ADC featuring a Vcm-based switching scheme and designed using a standard 65 nm CMOS process. Capacitor mismatches are detected by introducing a redundant bit, which evaluates the sign of the mismatch error. This error is then calibrated through a feedback loop using voltage dividers with four integrated memristors. These programmable voltage dividers generate a compensating voltage that is added to or subtracted from the ADC reference voltage (Vref) based on the sign of the mismatch error. Consequently, the adjusted Vrefcompensates the CDAC output level to reduce non-linearity induced by capacitor mismatches. Simulation results validate the feasibility of optimizing non-linearity in moderate/high-resolution SAR ADCs (12-bit in this study) caused by capacitor mismatches, improving the signal-to-noise-and-distortion ratio (SNDR) from 41.85 dB to 65.98 dB with memristor-assisted analog circuits. The proposed SAR ADC occupies 0.0153 mm2area according to the layout floorplan, making it a promising candidate for miniature/large-scale sensor interface application.

In addition to the conventional ADC design tradeoffs between power, speed, and accuracy, radiation tolerance is the fourth factor for ADCs used in radiation environments. This paper describes radiation-tolerant (RT) ADC design tradeoffs and design strategies. Then, the paper introduces a 13-bit RT pipelined-successive-approximation register (pipelined-SAR) ADC fabricated in 65 nm CMOS technology based on the concluded tradeoffs. To further improve the ADC power efficiency, a semi-time-interleaved (Semi-TI) structure is employed. Besides, the ping-pong auto-zeroing (AZ) scheme is implemented in the residue amplifier (RA) to reduce the TID-induced offset while maintaining low power dissipation. The proposed ADC is designed and hardened against Single Event Effects (SEEs) and Total Ionizing Dose (TID) effects from the structure to layout levels. All sub-blocks were examined, and only the critical blocks were hardened to avoid over-hardening. From the measurement results, the prototype ADC attains an 80 MS/s sampling rate and achieves 70.8-dB SNDR and 80.3-dB SFDR at the Nyquist input frequency. With a total power consumption of 13.8 mW, the prototype ADC establishes a state-of-the-art Walden Figure of Merit of 60.7 fJ/conv step, yielding an efficiency comparable to non-RT ADCs with similar specifications. Irradiation tests validate the consistent performance of the ADC up to a cumulative dose of 500 krad (Si) in X-ray testing, while laser testing indicates a robust SEE threshold and swift post-SEE recovery.

The linearity of the digital-to-analog converter (DAC) is a key bottleneck for high-resolution Sigma-Delta modulators that use multi-level quantizers. To address the DAC non-linearities caused by element mismatches and achieve a high signal-to-noise-and-distortion ratio (SNDR), this work exploits intrinsically linear capacitive DACs to improve the design of a high-resolution Sigma-Delta modulator with 4th-order, discrete-time architecture realized as a Cascade of Integrators with Feed Back (CIFB), and 3-level/5-level quantizers. The error due to capacitive element mismatch is mitigated by using an extra reference voltage and reconfiguring DAC topologies so that distortions brought by capacitor mismatches are largely reduced. We demonstrate in simulation results that a 128.9 dB modulator SNDR can be obtained in the presence of up to 1% DAC capacitance mismatch combined with 2% reference voltage variation, achieving 60 dB SNDR improvement compared with a design with a conventional DAC structure.

The natural similarity between the emerging memristive technology and synapses makes memristor a promising device in the spiking input based neuromorphic systems. However, while asynchronous signal processing relies on memristor's response under the pulses stimulus, hardly any memristor models take the impact of sequences features on device behaviour into account. This paper proposes an optimized data-driven compact memristor model where the boundary of its internal state variable-resistive state (RS) is modelled with pulse amplitude and pulse width based on characterisation data. The model has been developed in Verilog-A and verified in Cadence Virtuoso Electronic Design Automation (EDA) tools. Based on the simulation, we further introduce a new concept “Effective Time Window”. Along with the observed pulse width modulated resistance, more potential circuit applications can be implemented based on a more realistic memristor switching behaviour.

This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADCs). The scheme was implemented and validated in a 12-bit asynchronous successive approximation register (SAR) ADC, which consists of a hybrid binary weighted/R-2R digital-to-analog converter (binary/R-2R DAC) and other peripheral circuits. This hybrid DAC, in which one redundancy bit is introduced, is built with a memristor and standard polysilicon resistors. The proposed calibration technique can detect the errors caused by DAC mismatches and correct them by adjusting the resistance of the memristor (memristance) in a feedback loop. The implemented circuit takes the memristor’s advantages such as small area and resistance switching property. The proposed scheme has been designed and simulated in a standard 180 nm CMOS process. Eventually, a monolithic CMOS/memristor chip will be fabricated with the CMOS part processed at a standard foundry and the memristors integrated through post-CMOS processing in house. Simulation results demonstrate the feasibility of exploiting memristors to improve the linearity of high-resolution SAR ADCs. The designed calibration scheme can effectively reduce the integral non-linearity (INL) and differential non-linearity (DNL) of the 12-bit SAR ADC.

Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device’s resistance range to be between 1k$\Omega$ and 10M$\Omega$ with a minimum voltage range of ±1.5V on the device.

Epileptic seizure prediction could help patients stay safe and provide them with opportunities to prevent seizures in advance. This can be realised by a complete system that captures the intracortical neuronal signals from the implantable device, processes the recorded data for discriminating seizures and transfers the information to the personal advisory device. Seizures can be discriminated by monitoring the counts of population spikes and we proposed a spike detection front-end for this application. The proposed discrete-time system amplifies, detects and digitises the spiking with ultra-low power and high precision with the aid of memristor as a trimming device. In this paper, we utilised the measurement methodology for the discrete-time system that combines periodic steady-state analysis and transient simulation to examine its behaviour under sources of uncertainty: noise, process corner and mismatch. The noise performance can be improved by oversampling while maintaining low power consumption. And the memristive devices are capable of compensating the inherent offset and do not induce material impact. Combining work and verification above, the system can be scaled up and/or practical implementation in the next step.

One of the challenges of designing neural front-end is to reject the DC offset from electrodes. The conventional AC-coupled solution is to utilise large input capacitors and pseudo-resistors, which have the key limitations of area, linearity and DC drift. In this paper, we propose a DC-coupled solution based on the hybrid CMOS/memristor technique. The spike detection is realised by thresholding in the proposed front-end, which consists of a memristive amplifier and a DLC. The amplifier boosts micro-volt neural signals to milli-volt through integration, making it recognised by the DLC. In addition, the memristor is utilised as a trimming device along the current branch for the purpose of tuning the offset voltage. It is capable of compensating up to 50mV DC offset. With the oversampling ratio reaching 95, the accuracy spike detection can be maintained to 95% and the frontend consumes 123.5nW in our design example. The proposed DC offset front-end is capable of reaching high accuracy and low power consumption.

This paper presents the design and simulation results of a silicon cochlea system that has closely similar behavior as the real cochlea. A cochlea filter-bank based on the improved three-stage filter cascade structure is used to model the frequency decomposition function of the basilar membrane; a filter tuning block is designed to model the adaptive response of the cochlea; besides, an asynchronous event-triggered spike codec is employed as the system interface with bank-end spiking neural networks. As shown in the simulation results, the system has biologically faithful frequency response, impulse response, and active adaptation behavior; also the system outputs multiple band-pass channels of spikes from which the original sound input can be recovered. The proposed silicon cochlea is feasible for analog VLSI implementation so that it not only emulates the way that sounds are preprocessed in human ears but also is able match the compact physical size of a real cochlea.

This paper presents the design of a CMOS cochlea filter channel which achieves high tunability, sharp stopband cutoff and low power consumption with the use of floating active inductor (FAI) as the basic building block. Simulation results show that over 40dB of gain enhancement together with 20% frequency tuning can be achieved at the same time by adjusting only one circuit parameter. A fifth-order elliptic filter providing a stop-band slope of 65.4 ~ 139.8 dB/octave is used as the last stage of the cochlea filter. The power consumption of the cochlea filter channel is 86μW.

This paper proposes a low-noise MEMS interface circuit which has very small parasitic capacitance at the input node. The circuit presented is suitable for the MEMS cochlea-mimicking acoustic sensors which are highly parasitic-sensitive due to their low intrinsic sensing capacitance. In order to reduce the electronic noise of the interface circuit, chopper stabilization technique is implemented, and an effective method to optimize the critical transistor size for best noise performance is derived. Simulation results show that, for a MEMS sensing structure with 200 fF static capacitance, the interface circuit achieves a 0.72 aF equivalent capacitance noise floor over 100 Hz to 20 kHz audio bandwidth.

This paper presents the design of a spike event coded resonant gate transistor microphone system for neuromorphic auditory applications. The microphone system employs an array of resonant gate transistors (RGT) to transduce acoustic input directly into bandpass filtered analog outputs. The bandpass filtered analog outputs are encoded as spike time events by a spike event coder and are then transmitted asynchronously by using the Address Event Representation (AER) protocol. The microphone system is designed to receive external inputs in the spike time domain to actively control the RGT response, a feature not present in other MEMS microphone systems implemented so far. System level simulations showing the response of the RGT sensor model and its spike event coded response are presented.