With shrinking technologies and increasing design complexities, it is common to have a large number of modes (functional, scan, test and so on) and corners (PVT device and interconnect). This leads to an explosion in the number of scenarios (#modes × #corners) that need to be validated for timing. While multiple tactics are required to handle this problem, one essential way to address this is by reducing the number of modes by merging individual modes into superset modes. However, with the overriding necessity to maintain sign-off accuracy, mode merging with high merge-factor is very complex. In this paper, we propose a novel automated timing graph based approach to mode merging that is designed to meet these requirements. By construction, there is an inbuilt validation that the merged constraints correctly model the intent of original constraints. This technology is tested on large industrial designs and the results are provided.

The problem of calculating accurate impact of crosstalk on a circuit considering its inherent logic and timing properties is very complex. Although it has been widely studied, it still lacks an efficient solution. As a result, state–of–the–art crosstalk calculators use simplistic and overly pessimistic models resulting in the overestimation of crosstalk effects. Such pessimism in crosstalk analysis often leads to the triggering of false violations and consequently an inefficient use of design resources. The main contribution of this paper is a novel technique called Timing Arc Based Logic Analysis (TABLA) that serves as an efficient means to calculate realistic crosstalk bounds. TABLA uses timing arcs as basic elements to perform an efficient temporal logic analysis employing the min–max timing model using dedicated solvers for logic and timing. Additionally, a procedure to generate powerful conflict clauses is proposed to improve the run time of the overall analysis. The proposed technique has been tested in an industrial environment on benchmark circuits as well as on an industrial design, and results are provided.

Accurate estimation of worst-case crosstalk effects is critical for a realistic estimation of the worst-case behavior of deep sub-micron circuits. Crosstalk analysis models usually assume that the worst-case crosstalk occurs with all the aggressors of a victim (net or path) simultaneously inducing crosstalk even though this may not be possible at all. This overestimated crosstalk is called false noise. Logic correlations have been explored to reduce false noise in J.C. Beck, et al., (2004), which also used branch and bound method to solve the problem. In this paper, we propose a novel approach, named tendency graph approach (TGA), which preprocesses the logic constraints of the circuit to drastically speed up the fundamental branch and bound algorithm. The new approach has been implemented in C++ and tested on an industrial circuit in a current 90 nm technology, demonstrating that TGA considerably accelerates the solution to the false noise problem, and makes in many cases branch and bound feasible in the first place.