Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Benjamin Vogel

dblp:76/8291 · DBLP profile ↗
← Back
3ranked-venue papers
0as first author
0since 2021 · last 2016
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Energy-efficient computing · 36% Parallel and multicore computing · 36% Cloud and datacenter computing · 18%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Energy-efficient computing › power management
dynamic power management
0.212016
Scalable Power Management for On-Chip Systems with Malleable Applications · IEEE Trans. Computers 2016
Parallel and multicore computing › task scheduling
malleable jobs
0.212016
Scalable Power Management for On-Chip Systems with Malleable Applications · IEEE Trans. Computers 2016
Energy-efficient computing
power management
0.212016
Scalable Power Management for On-Chip Systems with Malleable Applications · IEEE Trans. Computers 2016
Parallel and multicore computing
processor allocation
0.212016
Scalable Power Management for On-Chip Systems with Malleable Applications · IEEE Trans. Computers 2016
Cloud and datacenter computing
resource management
0.212016
Scalable Power Management for On-Chip Systems with Malleable Applications · IEEE Trans. Computers 2016
Processor architecture and microarchitecture
multicore design
0.112016
Scalable Power Management for On-Chip Systems with Malleable Applications · IEEE Trans. Computers 2016
Integrated circuit design
system-on-chip
0.112016
Scalable Power Management for On-Chip Systems with Malleable Applications · IEEE Trans. Computers 2016

Methods — techniques the papers use, named apart from their topics

predictive modeling · 0.2
YearPublicationVenuePosition
2016 Scalable Power Management for On-Chip Systems with Malleable Applications
abstract
We present a scalable Dynamic Power Management (DPM) scheme where malleable applications may change their degree of parallelism at run time depending upon the workload and performance constraints. We employ a per-application predictive power manager that autonomously controls the power states of the cores with the goal of energy efficiency. Furthermore, our DPM allows the applications to lend their idle cores for a short time period to expedite other critical applications. In this way, it allows for application-level scalability, while aiming at the overall system energy optimization. Compared to state-of-the-art centralized and distributed power management approaches, we achieve up to 58 percent (average ≈15-20 percent) ED2P reduction.
Muhammad Shafique 0001, Anton Ivanov, Benjamin Vogel, Jörg Henkel
IEEE Trans. Computers3
2013 Self-adaptive hybrid dynamic power management for many-core systems
abstract
We present a self-adaptive, hybrid Dynamic Power Management (DPM) scheme for many-core systems that targets concurrently executing applications with what we call “expanding” and “shrinking” resource allocations as, for example, in [13]–[15] [27]. To avoid frequent allocation and de-allocation, it enables applications to temporarily reserve their resources and to perform local power management decisions. The expand-to-shrink time periods and resource demands are predicted on-the-fly based on the application-specific knowledge and the monitored system information. Experimental results demonstrate up to 15%-40% Energy-Delay2Product reduction of our scheme compared to state-of-the-art power management schemes like [4][8]. Self-adaptive local power-management decisions make our scheme scalable for large-scaled many-core systems as illustrated by numerous experiments.
Muhammad Shafique 0001, Benjamin Vogel, Jörg Henkel
DATE2
2012 Invasive manycore architectures
abstract
This paper introduces a scalable hardware and software platform applicable for demonstrating the benefits of the invasive computing paradigm. The hardware architecture consists of a heterogeneous, tile-based manycore structure while the software architecture comprises a multi-agent management layer underpinned by distributed runtime and OS services. The necessity for invasive-specific hardware assist functions is analytically shown and their integration into the overall manycore environment is described.
Jörg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hübner 0001, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe
ASP-DAC10