Wake-up receivers (WuRXs) help to cut down the average power consumed by the wireless devices in the Internet of things (IoT). Compared to the non-standard designs, the standard (e.g. BLE-compliant) WuRX chips can be integrated seamlessly into the widely-deployed infrastructures, while there are more design challenges since the BLE-compliant WuRX should be resilient to adjacent-channel interferes as well as realize a high sensitivity. In traditional BLE-compliant WuRXs, the interferes were suppressed by an FBAR filter or a low-noise local oscillator (LO) generator, with the penalty of sensitivity degradation or additional power consumption. The existing edge-combine LO generating method can cut down the power consumption, while the increased LO noise significantly degraded the signal-to-interference ratio (SIR) performance. In this work, we have demonstrated a BLE-compliant WuRX chip that improves both the SIR and sensitivity with low power dissipation. Instead of the conventional I/Q path with 90 degrees out of the phase, a pseudo-I/Q dual-downconversion structure is proposed to offer a WuRX driven by 120-degree-apart ultra-low-power LOs signals, which helps to improve the SIR performance due to the lower LO noise than the conventional edge-combine methods. In addition, a dummy down-converter based mismatch-cancellation technique is proposed to improve the image rejection ratio (IRR) and sensitivity. Fabricated by a 65nm CMOS process, the proposed BLE-compliant WuRX chip achieves -21dB SIR in the adjacent channel as well as -94dBm sensitivity at the cost of only$306\mu $W power.

The size of wireless systems is required to be reduced in many applications, such as ultra-low-power sensor nodes and wearable/implantable devices, where battery and crystal are the two main bottlenecks in system miniaturization. In recent years, battery-free radios based on wireless power transfer (WPT) have shown great potential in miniature wireless systems, while a reliable on-chip clock without a crystal remains a design challenge. Conventional methods utilized the RF WPT tone as the reference for clock generation, but the high RF frequency leads to high power consumption. In comparison, using a lower WPT frequency results in an antenna with a larger size. In this work, the$2^{\mathrm{nd}}$-order inter-modulation (IM2) component of the two RF WPT tones is extracted to lock an on-chip oscillator, providing a low-jitter PVT-robust clock. In this way, the wireless systems can benefit from: 1) The clock recovery circuits operate at a low IM2 frequency, reducing the power consumption. 2) The WPT can be set to a high RF frequency to minimize the antenna. Fabricated in 65 nm CMOS process, the proposed crystal-less clock generator takes a small area of 0.023 mm2 in a wireless system chip. Measured results show −92 dBc/Hz@10 kHz phase noise and 6.8$\mu \text{W}$power.