A joint design of message passing MIMO data detector/decoder with progressive parallel inter-carrier interference canceller (PPIC) based on factor graph for OFDM-based wireless communication systems is proposed. By exchanging messages both in space domain and frequency domain, the proposed algorithm can suppress inter-antenna interferences and cancel inter-carrier interferences iteratively and progressively. With a proper designed message passing schedule and random interleaver, the short cycle problem is solved. Computer simulations show that the performance of the proposed message passing MIMO detector outperforms MMSE-SIC MIMO detector. The performances of PPIC, both in perfect channel estimation and imperfect channel estimation cases, are compared with the standard PIC architecture and the ICI self-canceller. The proposed PPIC is superior to PIC both in computational complexity and system architecture. The parallel structure of PPIC is similar to a systolic array. The proposed algorithm potentially leads to a very-high-speed detector/decoder. It is very suitable for VLSI implementation and it is a potential candidate for data detection/decoding in future high data rate, high mobility, wireless MIMO-OFDM communication systems.

A low complexity 3-stage parallel interference cancellation (LCPIC) receiver for DS-CDMA cellular systems is proposed and analyzed. Based on numerical analyses, the power efficiency of the LCPIC receiver is close to that of the 3-stage PIC receiver and better than that of the 2-stage PIC receiver in AWGN with either perfect power control or log-normal power control error. In addition, the near-far resistance of the LCPIC, 2-stage, 3-stage PIC, and SIC receivers are analogous since their performances are undistinguishable in near-far channels. Still more, the computational complexity, which is in terms of the needs of flops per bit decision, of the LCPIC receiver is much less than that of the 3-stage PIC receiver and only a little more than that of the 2-stage PIC receiver.

A programmable pipelined digital differential matched filter (PDMF) implemented for a direct sequence spread spectrum receiver is proposed in this paper. To reduce the power consumption, the PDMF architecture is based on the synchronization combined PN code phase acquisition algorithm. Compared with the conventional PN code phase acquisition algorithm, the theoretical analysis result indicates that the PDMF acquires both power efficient and preferable detection. Depending on different applications, programmability allows the PDMF to implement 3-tap, 5-tap, or 11-tap Barker codes with the same hardware but different precisions for each tap coefficient. For short tap Baker codes, the architecture could adopt more precision on each tap coefficient to resist the channel noise. Simulation results also show that there are fewer errors of high sample precision with the same tape.