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Sharon R. Perkins

dblp:77/1008 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1988
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › logic synthesis
logic minimization		 0.011988
An algorithm for identifying and selecting the primed implicants of a multiple-output Boolean function · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988
Electronic design automation
logic synthesis		 0.011988
An algorithm for identifying and selecting the primed implicants of a multiple-output Boolean function · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988
Electronic design automation › logic synthesis › two-level logic minimization
prime implicant selection		 0.011988
An algorithm for identifying and selecting the primed implicants of a multiple-output Boolean function · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988

Methods — techniques the papers use, named apart from their topics

directed-search algorithm · 0.0
YearPublicationVenuePosition
1988 An algorithm for identifying and selecting the primed implicants of a multiple-output Boolean function
abstract
A multiple-output Boolean minimization procedure is presented that generates a minimum cover with computational efficiency by extending the directed search algorithm to the multiple-output case. This procedure is applicable to manual execution as well as to automated execution, and to both conventional two-level gating structures and programmable logic arrays (PLAs).>
Sharon R. Perkins, Tom Rhyne
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1