The estimation of maximum and minimum leakage consumption for nominal values of the processing parameters is addressed. Tight upper and lower bounds of both extremes are found. In addition, input vectors producing a consumption close to these extremes are obtained. To solve this NP-complete problem, a new hierarchical method based on automatic test pattern generation (ATPG) tools is proposed. The results obtained are compared with Monte Carlo simulations and alternative approaches based. on other heuristics. The results obtained show that the maximum and minimum leakage consumption is estimated with an error lower than 8%. For the largest circuits, c6288 and c7552, the maximum error is lower than 1.3%. The results show that the method compares favorably with alternative approaches.

The effectiveness of I/sub DDQ/ testing requires appropriate discriminability of defective and non-defective quiescent currents. Consequently, the interest in characterizing these currents is growing. In this paper we focus our attention on the non-defective I/sub DDQ/ current characterization. The dependence of I/sub DDQ/ on the channel length spread in scaled down devices is examined. The I/sub DDQ/ distribution of a subthreshold current dominant technology is obtained. Finally, I/sub DDQ/ test limits depending on acceptable yield loss and standard deviation of the channel length are determined.

The quiescent current (I/sub DDQ/) consumed by an IC is a good indicator of the presence of a large of defects. However, the effectiveness of I/sub DDQ/ testing requires appropriate discriminability of defective and defect-free currents and hence it becomes necessary to estimate the currents involved in order to design the I/sub DDQ/ sensing circuitry. In this work, we present a method to estimate the non-defective I/sub DDQ/ consumption based on a hierarchical approach using layout (device), electrical (cell) and logic (circuit) information. The maximum of the defect-free I/sub DDQ/ is obtained with a technique based on ATPG. The results show that the proposed method gives the maximum defect-free I/sub DDQ/ for small circuits. For large circuits, heuristics to find lower and upper bounds of the maximum defect-free I/sub DDQ/ are presented. Uncertainty margins lower than 15% have been found in the circuits experimented on.