• Understand biomolecular systems through their motions •Numerical integration of Newton's laws of motion — Model atoms as point masses — Compute forces on every atom based on current positions — Update atom velocities and positions in discrete time steps of a few femtoseconds • Force computation described by a model: the force field

Anton 3 is the newest member in a family of supercomputers specially designed for atomic-level simulation of molecules relevant to biology (e.g., DNA, proteins, and drug molecules). Anton 3 achieves order-of-magnitude improvements in time-to-solution over its predecessor, Anton 2 (the current state of the art), and is over 100-fold faster than any other currently available supercomputer, thereby enabling broad new avenues of research on critical questions in biology and drug discovery. This speedup means that a 512-node Anton 3 simulates a million atoms at over 100 microseconds per day. Furthermore, Anton 3 attains this performance while consuming an order of magnitude less energy per simulated microsecond than any other machine. Like its predecessors, Anton 3 was designed from the ground up around a new custom chip to best exploit the capabilities offered by new technologies. We present here the main architectural and algorithmic developments that were necessary to achieve such significant advances.

The accurate analysis of cross-talk noise in VLSI chips must consider the timing when signals can interfere, i.e., the switching windows. It is important to determine the time-alignment of signal switching events that cause maximal cross-talk noise. Moreover, it is necessary to include the effects of process and environmental variations, as they strongly affect the switching windows, and further complicate the computation of the worst possible noise. We present a general formulation of the worst case noise analysis problem as a mixed-integer-linear-program, (MILP). The formulation captures elaborate cross-talk models that include variational switching windows, victim sensitivity windows, discontinuous switching windows, diversely shaped noise pulses, and logic constraints on switching activity. We demonstrate that our technique correctly predicts the worst noise pulse, including cases even where conventional approaches fail.

Transient analysis of large-scale power delivery network (PDN) is a critical task to ensure the functional correctness and desired performance of today's integrated circuits (ICs), especially if significant transient noises are induced by clock and/or power gating due to the utilization of extensive power management. In this paper, we propose an efficient algorithm for PDN transient analysis based on sparse approximation. The key idea is to exploit the fact that the transient response caused by clock/power gating is often localized and the voltages at many other “inactive” nodes are almost unchanged, thereby rendering a unique sparse structure. By taking advantage of the underlying sparsity of the solution structure, a modified conjugate gradient algorithm is developed and tuned to efficiently solve the PDN analysis problem with low computational cost. Our numerical experiments based on standard benchmarks demonstrate that the proposed transient analysis with sparse approximation offers up to 2.2× runtime speedup over other traditional methods, while simultaneously achieving similar accuracy.

Sensitivities of the dynamic system responses with respect to the system parameters are highly valuable, with broad applications such as system tuning and uncertainty quantification. Compared to the direct methods, adjoint methods are much more efficient when the number of parameters is large. In this paper, we present a time-unrolling method to compute adjoint sensitivities. Instead of explicitly constructing the adjoint system, which quite often is nontrivial, our time-unrolling method implicitly retrace the response trajectory by utilizing the fitting polynomial of the integration methods. This paper provides theoretical foundation of the method as well as experimental demonstrations of its effectiveness.

Shooting, finite difference, or harmonic balance techniques in conjunction with a damped Newton method are widely employed for the numerical calculation of limit cycles of (free-running, autonomous) oscillators. In some cases, however, nonconvergence occurs when the initial estimate of the solution is not close enough to the exact one. Generally, the higher the quality factor of the oscillator the tighter are the constraints for the initial estimate. A 2-D homotopy method is presented in this paper that overcomes this problem. The resulting linear set of equations is underdetermined, leading to a nullspace of rank two. This underdetermined system is solved in a least squares sense for which a rigorous mathematical basis can be derived. An efficient algorithm for solving the least squares problem is derived where sparse matrix techniques can be used. As continuation methods are only employed for obtaining a sufficient initial guess of the limit cycle, a coarse grid discretization is sufficient to make the method runtime efficient.

This paper described a model-order reduction (MOR) method based on a novel pure-nodal analysis formulation (PNA) which permits the use of symmetric, positive-definite Cholesky solvers for all circuit topologies. Moreover, frequently occurring special cases, e.g., inductor-resistor tree structures result in particular types of matrices that are solved by an even faster linear time algorithm. The model order reduction algorithms also uses symmetric-Lanczos iteration and non- standard inner-products for generating the Krylov subspace basis. Its efficiency is supported by a wide range of industrial examples.

Abstract---Static timing analysis of VLSI circuits relies on tabular models of logic gates obtained during library characterization. At characterization time logic gates are simulated at the circuit level with a range of input waveforms (e.g., saturated ramps with different slews) and various output loads. At timing analysis time the same gates are driven by input waveforms that differ from the class of characterization waveforms. This paper proposes a method for mapping the waveforms that arise in static timing analysis to members of the class of waveforms used to characterize gate timing performance during library characterization. The method is based on the moments of the input waveform, which describe concisely the salient features of the waveform. The mapping between the input waveform and the effective characterization waveform is accomplished by positing functional relationships between the input waveform’s moments and the parameters of the characterization waveform. The unknown coefficients of this functional relationship are determined by minimizing the worst case error of the output waveform over a representative set of input waveforms and gate loads. The technique requires no change to the library characterization procedure, and minimal change to the static timing tool with little to no additional computational burden on the timer.

This paper describes a waveform compression technique suitable for the efficient utilization, storage and interchange of the emerging current source model (CSM) based cell libraries. The technique is based on pre-processing of a collection of voltage/current waveforms for the cells in the library and then, constructing an orthogonal time-voltage/time-current waveform basis using singular-value decomposition. Compression is achieved by representing all waveforms as linear combination coefficients of adaptive subset of the basis waveforms. Experimental results indicate that adaptive waveform representation results in higher compression ratios than the waveform representation as a function of fixed set of basis functions. Interpolation and further compression are obtained by representing the coefficients as simple functions of various parameters, e.g., input slew, load capacitance, supply voltage, and temperature. The methods introduced in this paper are tested and validated on several industrial strength libraries, with spectacular compression results.

Timing, noise, and power analysis have historically relied on high level, black-box, non-physical logic library models. Moreover, these models were of a look-up type, i.e. precharacterized for practically all the possible environments in which they would be eventually used. The evolution of the VLSI technology towards nanometer sized features made this characterization methodology impractical. Increasingly, the space of all possible environments grew too rich to be fully covered during characterization. In the past decade, the so-called effective capacitance was introduced to provide some analysis capability to gate models, i.e., the ability to evaluate in the presence of RC loads, although characterized with capacitive loads only. In current and future VLSI technologies, such simple extensions no longer provide the required accuracy. Increasingly, models of logic gates must retain elements of the electrical behavior of the circuit in order to provide accurate timing, noise, and power information. This poses a new challenge on the analysis algorithms, now required to handle an enhanced level of detail in modeling without significantly degrading the overall efficiency of the application.

This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs formalize a class of gate models which include the existing industry standards, such as CCS and ECSM driver models as special cases. The analysis technique relies on primary MVTM characterization data and does not require explicit instantiation of controlled current source models. Therefore, the method is more accurate, efficient, and general than traditional transient analysis. The theoretical results are validated by detailed simulations and use within full chip timing analysis.

The simulation of circuits containing silicon-on-insulator (SOI) transistors encounters specific difficulties mainly due to the presence of the insulated body nodes, i.e., connected by high impedance connections with the rest of the circuit. These high impedance connections cause the charges stored in transistor body nodes to change at much slower rates than the normal operation of the circuit. Therefore the short term operation of a circuit will be strongly dependent on the state of the SOI transistor body charge, which in turn depends on the activity of the transistor during thousands of the previous cycles: the history effect. The presence of high impedance connections has another adverse effect on the simulation of such circuits: circuit matrices become severely ill-conditioned, thus slowing down or even compromising the convergence of the initial DC solution. In this paper, we are introducing the novel non-equilibrium, initial condition analysis (NEICA), as the preferred initialization method for circuits containing SOI devices. This method allows the user full control of the initial state of the SOI devices, preserves full insight into the physical phenomenon, and leads to a well-conditioned and thus reliable transient analysis initialization problem. The method is easily implemented in most existing circuit simulation programs and facilitates other important applications beyond the analysis of SOI transistor circuits. ESD analysis, and simulation of the effects of charged particles hitting circuits, are just two such examples

This paper addresses the well known difficulty of applying model order reduction (MOR) to linear circuits with a large number of input-output terminals. Traditional MOR techniques substitute the original large but sparse matrices used in the mathematical modeling of linear circuits by models that approximate the behavior of the circuit at its terminals, and use significantly smaller matrices. Unfortunately these small MOR matrices become dense as the number of terminals increases, thus canceling the benefits of size reduction. The paper introduces a model reduction technique suitable for circuits with numerous terminals. The technique exploits the correlation that almost always exists between circuit responses at different terminals. The correlation is rendered explicit through an SVD-based algorithm and the result is a substantial sparsification of the MOR matrices. The proposed sparsification technique is applicable to a large class of problems encountered in the analysis and design of interconnect in VLSI circuits. Relevant examples are used to analyze and validate the method.

In the process of designing state-of-the art VLSI circuit we often encounter large but highly structured linear subcircuits with large number of terminals. Classical examples are power supply networks, clock distribution networks, large data buses, etc. Various applications would benefit from efficient high level models of such networks. Unfortunately the existing model-order-reduction algorithms are not adapted to handle more than a few tens of terminals. This talk introduces RecMOR, an algorithm for the computation of reduced order models of structured linear circuits with numerous I/O ports. The algorithm exploits certain regularities of the subcircuit response that are typical in numerous applications of interest. When these regularities are present, the normally dense matrix-transfer function of the subcircuit contains sub-blocks that in some sense are significantly low rank and can be compactly modeled by the recently introduced SVDMOR algorithm. The new RecMOR algorithm decomposes the large matrix-transfer function recursively, and applies SVDMOR compression adaptively to the sub-blocks of the transfer function. The result is a reduced order model that is sparse, efficient, and directly usable as an efficient substitute of the subcircuit in circuit simulations. The method is illustrated on several circuit examples.

Shooting, finite difference or Harmonic Balance techniques in conjunction with Newton's method are widely employed for the numerical calculation of limit cycles of oscillators. The resulting set of nonlinear equations are normally solved by damped Newton's method. In some cases however divergence occurs when the initial estimate of the solution is not close enough to the exact one. A two-dimensional homotopy method is presented in this paper which overcomes this problem. The resulting linear set of equations employing Newton's method is under-determined and is solved in a least squares sense for which a rigorous mathematical basis can be derived.

Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable to predict the rate of occasional detection errors and the loss of synchronization due to the non-ideal operation of such circuits. In high-speed data networks, the bit-error-rate specification on the system can be very stringent, i.e., 10/sup -14/. It is not feasible to predict such error rates with straightforward, simulation based, approaches. This work introduces a stochastic model and an efficient, analysis-based, non-Monte-Carlo method for performance evaluation of digital data and clock recovery circuits. The analyzed circuit is modeled as finite state machines with inputs described as functions on a Markov chain state-space. System performance measures, such as probability of bit errors and rate of synchronization loss, can be evaluated through the analysis of a larger resulting Markov system. A dedicated multi-grid method is used to solve the very large associated linear systems. The method is illustrated on a real industrial clock-recovery circuit design.

This paper introduces a novel, discrete optimization based method for the computation of coarsely quantized, oversampled finite-length digital signals. The method, while only suitable for off line computation, is more general than the established sigma-delta encoding technique, due to its capacity to take into account complex specifications and design trade-offs. Signal generation is formulated as a linearly constrained, convex, integer quadratic programming problem which is solved through an application specific branch-and-bound algorithm. The optimization method is illustrated with a fractional-N frequency synthesizer based modulator design example.

In high-speed data networks, the bit-error-rate specification on the system can be very stringent, i.e., 10/sup -4/. At such error rates, it is not feasible to evaluate the performance of a design using straightforward, simulation based, approaches. Nevertheless performance prediction before actual hardware is built is essential for the design process. This work introduces a stochastic model and an analysis-based, nonMonte-Carlo method for performance evaluation of digital data communication circuits. The analyzed circuit is modeled by a number of interacting finite state machines with inputs described as functions on a Markov chain state-space. The composition of these elements results in a typically very large Markov chain. System performance measures, such as probability of bit errors and rate of synchronization loss, can be evaluated by solving linear problems involving the large Markov chain's transition probability matrix. This paper first describes a dedicated multi-grid method used to solve these very large linear problems. The principal bottleneck in such an approach is the size of the Markov chain state-space, which grows exponentially with system complexity. The second part of this paper introduces a novel, graph based, data structure capable of efficiently storing and manipulating transition probability matrices for several million state Markov chains. The methods are illustrated on a real industrial clock-recovery circuit design.

Modern IC design requires accurate analysis and modeling of chip-level interconnect, the substrate and package parasitics. Traditional approaches for such analyses are computationally expensive. In this paper we discuss some recent novel schemes for extraction and reduced order modeling that help overcome this computational bottleneck.

Interconnect parasitics are playing a dominant role in determining chip performance and functionality in deep-submicron designs. This problem is compounded by increasing chip frequencies and design complexity. As parasitic coupling capacitances are a significant portion of total capacitance in deep-submicron designs, verification of both performance and functionality assumes greater importance. This paper describes techniques for the modeling and analysis of parasitic coupling effects for large VLSI designs. Analysis results from a controlled experimental setup are presented to show the need for accurate cell models. Results from application of these techniques on a lending edge Digital Signal Processor (DSP) design are presented. Accuracy comparison with detailed SPICE-level analysis is included.

Introduces a methodology for the evaluation of the interference noise caused by digital switching activity in sensitive circuits of a mixed digital-analog chip. The digital switching activity is modeled stochastically as functions defined on Markov chains. The actual interference signal is obtained through the modulation of this discrete stochastic signal with real current injection patterns stored a priori in a pre-characterized library. The interference noise results from the propagation of these continuous stochastic signals through the linear network that models the chip power grid, substrate and relevant package parasitics. The interference noise power spectral density is computed by linear frequency-domain analysis. The methodology is implemented using advanced numerical techniques that are capable of tackling very large problems.

We describe powerful new techniques for the analysis of RF circuits. Next-generation CAD tools based on such techniques should enable RF designers to obtain a more accurate picture of how their circuits will operate. These new simulation capabilities will be essential in order to reduce the number of design iterations needed to produce complex RF ICs. 1 Introduction Design methodology and superior computer-aided design tools are key to success in the integrated circuit (IC) business. They are particularly important in the case of radio-frequency (RF) IC applications, where the digital IC divide-and-conquerdesign style, based on partitioning by functional blocks and abstraction levels, does not apply. The goal of an RF designer is to get a manufacturable design that meets the specifications with minimum cost, under severe time-to-market constraints. Unlike traditional discretecomponent RF design, prototyping is practically impossible, and the validation of a design can only be done b...

This paper introduces SyMPVL, an algorithm for the approximation of the symmetric multi-port transfer function of an RLC circuit. The algorithm employs a symmetric block-Lanczos algorithm to reduce the original circuit matrices to a pair of typically much smaller, banded, symmetric matrices. These matrices determine a matrix-Pade approximation of the multi-port transfer function, and can serve as a reduced-order model of the original circuit. They can be "stamped" directly into the Jacobian matrix of a SPICE-type circuit simulator, or can be used to synthesize an equivalent smaller circuit. We also prove stability and passivity of the reduced-order models in the RL, RC, and LC special cases, and report numerical results for SyMPVL applied to example circuits.

A new technique is presented for computing noise in nonlinear circuits. The method is based on a formulation that uses harmonic power spectral densities (HPSDs), using which a block-structured matrix relation between the second-order statistics of noise within a circuit is derived. The HPSD formulation is used to devise a harmonic-balance-based noise algorithm that requires O(nN log N) time and O(nN) memory, where n represents circuit size and N the number of harmonics of the large-signal steady state. The method treats device noise sources with arbitrarily shaped PSDs (including thermal, shot and flicker noises) handles noise input correlations and computes correlations between different outputs. The HPSD formulation is also used to establish the non-intuitive result that bandpass filtering of cyclostationary noise can result in stationary noise. The new technique is illustrated using an example that exhibits noise folding and interaction between harmonic PSD components. The results are validated against Monte-Carlo simulations. The noise performance of a large industrial integrated RF circuit (with >300 nodes) is also analyzed in less than 2 hours using the new method.

This paper introduces a new circuit noise analysis and modeling method. The noise analysis method computes an analytic expression of frequency, in rational form, which represents the Pade approximation of the noise power spectral density. The approximation can be carried out efficiently, to the required accuracy, using a variant of the PVL or MPVL algorithms. The new method is significantly more efficient than traditional methods for noise computation, at numerous frequency points. In addition, it allows for a compact and cascadable modeling of noise that can be used in system level simulations.

This paper discusses the analysis of large linear electrical networks consisting of passive components, such as resistors, capacitors, inductors, and transformers. Such networks admit a symmetric formulation of their circuit equations. We introduce SyPVL, an efficient and numerically stable algorithm for the computation of reduced-order models of large, linear, passive networks. SyPVL represents the specialization of the more general PVL algorithm, to symmetric problems. Besides the gain in efficiency over PVL, SyPVL also preserves the symmetry of the problem, and, as a consequence, can often guarantee the stability of the resulting reduced-order models. Moreover, these reduced-order models can be synthesized as actual physical circuits, thus facilitating compatibility with existing analysis tools. The application of SyPVL is illustrated with two interconnect-analysis examples.

A method for the e�cient computation of accu� rate reduced�order models of large linear circuits is de� scribed. The method � called MPVL � employs a novel block Lanczos algorithm to compute matrix Pad�e ap� proximations of matrix�valued network transfer func� tions. The reduced�order models � computed to the re� quired level of accuracy � are used tospeed up the anal� ysis of circuits containing large linear blocks. The lin� ear blocks are replaced by their reduced�order models� and the resulting smaller circuit can be analyzed with general�purpose simulators � with signi�cant savings in simulation time and � practically � no loss of accuracy. 1

In this paper, we introduce PVL, an algorithm for computing the Pade approximation of Laplace-domain transfer functions of large linear networks via a Lanczos process. The PVL algorithm has significantly superior numerical stability, while retaining the same efficiency as algorithms that compute the Pade approximation directly through moment matching, such as AWE and its derivatives. As a consequence, it produces more accurate and higher-order approximations, and it renders unnecessary many of the heuristics that AWE and its derivatives had to employ. The algorithm also computes an error bound that permits to identify the true poles and zeros of the original network. We present results of numerical experiments with the PVL algorithm for several large examples.>

A novel formulation of the parametric yield as a surface integral on the boundary of the disturbance space acceptability region is introduced. This formulation allows the accurate and efficient estimation of yield via a Monte Carlo method which can also produce yield gradients with minimal overhead. The authors extend this formulation to a more general IC quality measure. A general IC quality optimization method, significantly more efficient than Taguchi's, is introduced. This method can handle multiple performances and perform yield maximization as a special case. The optimization method is demonstrated on several circuit examples.>

Automatic differentiation as a technique for accurate and reliable computation of partial derivatives in device models used by circuit simulation is introduced. The requirements for derivative computations in several simulation algorithms are reviewed, and two automatic differentiation methods are discussed. The application of automatic differentiation to circuit simulation and device modeling is demonstrated through several circuit analysis examples.>

An analog simulation environment based on the C/sup ++/ language is described. Not only is the system written in C/sup ++/, but also C/sup ++/ is used as the circuit description language. This arrangement provides an unusual level of convenience and efficiency for manipulating simulation results. Automatic differentiation techniques, using the operator overloading facility of C/sup ++/, lead to compact modeling subroutines and allow sensitivity computations to be integrated smoothly into other analyses. The architecture of the simulator and efficiency considerations are discussed.>

A novel formulation of the parametric yield as a surface integral on the boundary of the disturbance space acceptability region is introduced. This formulation allows the accurate and efficient estimation of yield via a Monte Carlo method which can also produce yield gradients with minimal overhead. Under mild assumptions, the surface integral based yield estimate is continuous and practically twice differentiable almost everywhere; therefore it is ideally suited for use with powerful gradient-based optimization algorithms. A general IC quality optimization method, significantly more efficient than Taguchi's method, is also introduced. This method can handle multiple performances and handles yield maximization as a special case.>

Both direct and adjoint methods are applied to the computation of time-domain transient sensitivities in the already efficient SPECS piecewise approximate circuit simulation environment. By exploiting the event-driven nature of SPECS, the computation, storage, and interpolation of the Jacobians that specify the appropriate linearized circuit during the forward simulation is not required to obtain sensitivities. Both direct and adjoint methods require only a marginal computational overhead and provide equivalent results. The choice of the method to use depends on the ratio of the number of outputs to the number of parameters. More parameters favor the adjoint method and more outputs favor the direct. The overall efficiency of both SPECS and its time-domain sensitivity extension allows it to be applied to realistic circuits that, due to their large size, had previously made such analysis impractical. Simulation results on industrial circuits of up to 1500 MOS transistors show that transient sensitivities can be efficiently computed for large circuits.>

A method is described for estimating the yield and yield gradient based on a priori geometric approximation of the acceptability region in the disturbance space. Circuit performance macromodeling is used to construct the acceptability region approximation. While yield evaluation can be carried out in either the performance space or parameter space, it is shown that for monolithic integrated circuits, the gradient of yield can only be estimated accurately in the disturbance space.>

The incorporation of inductors in a piecewise approximate circuit simulator, enhancing the generality of such a tool, is presented. Most approximate timing simulators preclude inductors from the underlying circuit. Conventional simulators allow inductive effects, but are too inefficient to simulate very large circuits. The formulation presented allows the event-driven simulation of circuits containing inductors, capacitors and general nonlinear elements. The event processing algorithm is based on the conservation of flux and energy. The implementation was tested in a prototype addition to the SPECS simulation environment. In addition, the theory behind the incorporation of mutual inductors is presented. A few benchmarks were run to confirm the veracity of the model. Research into the automatic, dynamic determination of the optimum current resolution would cause the tool to be more efficient, as well as relieve the designer of choosing a current resolution for the inductors in the circuit.>

Transient sensitivity computation in SPECS (simulation program for electronic circuits and systems), which provides a unique capability both to enhance efficiency and to validate simulation results, is described. By using transient sensitivities with respect to the entries of piecewise constant (table) element models and suppressed parasitics, an initially crude and correspondingly quick simulation can be undertaken and then augmented if necessary for improved accuracy. More specifically, table models are refined and parasitics reintroduced only where required in the final analysis as indicated by sensitivity results. This overall approach increases confidence in the results of the SPECS simulation strategy which relies heavily on simplified models for its enhanced efficiency.>