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Yao-Ping Chen

dblp:77/1771 · DBLP profile ↗
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8ranked-venue papers
6as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 8 · 6 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design
interconnect optimization
0.011996
Optimal Wire-Sizing Formular Under the Elmore Delay Model · DAC 1996
Electronic design automation
physical design
0.011996
Optimal Wire-Sizing Formular Under the Elmore Delay Model · DAC 1996
Electronic design automation › physical design › interconnect optimization
wire sizing
0.011996
Optimal Wire-Sizing Formular Under the Elmore Delay Model · DAC 1996
Electronic design automation › timing analysis › interconnect delay estimation
elmore delay
0.011996
Optimal Wire-Sizing Formular Under the Elmore Delay Model · DAC 1996
Electronic design automation
timing analysis
0.011996
Optimal Wire-Sizing Formular Under the Elmore Delay Model · DAC 1996

Methods — techniques the papers use, named apart from their topics

elmore delay model · 0.0analytical optimization · 0.0
YearPublicationVenuePosition
1997 Clustering and Load Balancing for Buffered Clock Tree Synthesis
abstract
Buffers in clock trees introduce two additional sources of skew: the first source of skew is the effect of process variations on buffer delays. The second source of skew is the imbalance in buffer loading. We propose a buffered clock tree synthesis methodology whereby we first apply a clustering algorithm to obtain clusters of approximately equal capacitance loading. We drive each of these clusters with identical buffers. A sensitivity based approach is then used for equalizing the Elmore delay from the buffer output to all of the clock nodes. The skew due to load imbalance is minimized concurrently by matching a higher-order model of the load by wire sizing and wire lengthening. We demonstrate how this algorithm can be used recursively to generate low-skew buffered clock trees.
Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, Martin D. F. Wong, Lawrence T. Pileggi
ICCD2
1997 On retiming for FPGA logic module minimization
Yao-Ping Chen, Martin D. F. Wong
Integr.1
1997 A graph theoretic approach to feed-through pin assignment
Yao-Ping Chen, Martin D. F. Wong
Integr.1
1996 Optimal Wire-Sizing Formular Under the Elmore Delay Model
abstract
In this paper, we consider non-uniform wire-sizing.Given a wire s e gment of length L, let f(x) be the width of the wire at position x, 0 x L .We show that the optimal wiresizing function that minimizes the Elmore delay through the wire i s f ( x ) = ae bx , where a > 0 and b > 0 are c onstants that can be c omputed i n O (1) time.In the case where lower bound (L > 0 ) and upper bound (U > 0 ) on the wire widths are given, we show that the optimal wire-sizing function f(x) is a truncated version of ae bx that can also be determined i n O (1) time.Our wire-sizing formula can be iteratively applied to optimally size the wire s e gments in a routing tree.
Charlie Chung-Ping Chen, Yao-Ping Chen, Martin D. F. Wong
DAC2
1995 A Graph Theoretic Approach to Feed-Through Pin Assignment
Yao-Ping Chen, Martin D. F. Wong
ISCAS1
1994 On Retiming for FPGA Logic Module Minimization
abstract
We consider the problem of minimizing the number of logic modules for Actel 2 or Actel 3 sequential circuits. We make use of the fact that if a flip-flop is the only destination of its driving combinational block, then both the flip-flop and the combinational block can be put in a sequential module. Retiming technique is applied to minimize the number of resistors that can not be merged with combinational blocks. We formulate the problem as an integer linear program. We show that the constraint matrix of the integer program is totally unimodular. As a result, we can solve our logic module minimization problem optimally by solving the linear relaxation of the integer program.>
Yao-Ping Chen, Martin D. F. Wong
ICCD1
1993 On optimal approximation of orthogonal polygons
Yao-Ping Chen, Martin D. F. Wong
ISCAS1
1993 A Graph Partitioning Problem for Multiple-chip Design
Yao-Ping Chen, Ting-Chi Wang, Martin D. F. Wong
ISCAS1