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Kun Qian 0014

dblp:77/2062-14 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2011
0000-0001-7429-1742ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 75% Performance modeling and evaluation · 20% Hardware reliability and fault tolerance · 5%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › design for manufacturability › statistical design › statistical circuit design
spatial variation modeling		 0.222011
Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability · DAC 2009
Electronic design automation › timing analysis
statistical timing analysis		 0.122011
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability · DAC 2009
Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011
Performance modeling and evaluation
statistical analysis		 0.112011
Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011
Electronic design automation
power estimation		 0.012011
Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011
Electronic design automation › power estimation
statistical leakage analysis		 0.012011
Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011
Electronic design automation
timing analysis		 0.012011
Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011
Hardware reliability and fault tolerance
process variation		 0.012009
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability · DAC 2009

Methods — techniques the papers use, named apart from their topics

spatial correlation modeling · 0.1monte carlo analysis · 0.1analytical modeling · 0.1
YearPublicationVenuePosition
2011 Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability
abstract
Modeling spatial variation is important for statistical analysis. Most existing works model spatial variation as spatially correlated random variables. We discuss process origins of spatial variability, all of which indicate that spatial variation comes from deterministic across-wafer variation, and purely random spatial variation is not significant. We analytically study the impact of across-wafer variation and show how it gives an appearance of correlation. We have developed a new die-level variation model considering deterministic across-wafer variation and derived the range of conditions under which ignoring spatial variation altogether may be acceptable. Experimental results show that for statistical timing and leakage analysis, our model is within 2% and 5% error from exact simulation result, respectively, while the error of the existing distance-based spatial variation model is up to 6.5% and 17%, respectively. Moreover, our new model is also faster than the spatial variation model for statistical timing analysis and faster for statistical leakage analysis.
Lerong Cheng, Puneet Gupta 0001, Costas J. Spanos, Kun Qian 0014, Lei He 0001
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4
2009 Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability
abstract
Modeling spatial variation is important for statistical analysis. Most existing works model spatial variation as spatially correlated random variables. We discuss process origins of spatial variability, all of which indicate that spatial variation comes from deterministic across-wafer variation, and purely random spatial variation is not significant. We analytically study the impact of across-wafer variation and show how it gives an appearance of correlation. We have developed a new dielevel variation model considering deterministic across-wafer variation and derived the range of conditions under which ignoring spatial variation altogether may be acceptable. Experimental results show that our model is within 1% error from exact simulation result while the error of the existing distance-based spatial variation model is up to 8%. Moreover, our new model is also 10X faster than the spatial variation model for Monte-Carlo analysis.
Lerong Cheng, Puneet Gupta 0001, Costas J. Spanos, Kun Qian 0014, Lei He 0001
 DAC4