The three dimensional circuit (3-D-IC) achieves high performance by stacking several layers of active electronic components vertically. Despite its impact on performance improvement, 3-D-IC also brings great challenges to chip thermal management due to its high heat density. Microchannel-based liquid cooling shows great potential in removing the high density heat inside 3-D circuits. The current microchannel heat sink designs spread the entire surface to be cooled with microchannels. This approach, though it provides sufficient cooling, consumes significant amount of extra cooling power. In this paper, we investigate the design of non-uniformly distributed microchannel cooling systems which provide sufficient cooling with less cooling power. The experiments show that, compared with the conventional design which spreads microchannels all over the chip, our non-uniform microchannel design achieves up to 80% cooling power savings.

Thermal/power issues have become increasingly important with more and more transistors being placed on a single chip. Many dynamic thermal/power management techniques have been proposed to address such issues but they all depend heavily on accurate knowledge of the chip's thermal state during runtime. In this paper, we describe a unified statistical framework for designing an on-chip thermal sensing infrastructure that can be used to track the chip's thermal state at runtime. Specifically, we address the following problems in this statistical framework: 1) sensor placement; 2) sensor data compression; 3) sensor data fusion; and 4) overall interplay. Our methods exploit the correlations between temperatures in different parts of the chip to drive sensor placement, data compression, and data fusion in both noiseless and noisy sensor cases. Our framework is also capable of choosing the appropriate degree of compression for each sensor while accounting for their local space constraints during deployment. The experimental results show that the root-mean-square error of the thermal estimates produced by our sensing infrastructure is on average 35% better than an equivalent system that uses a range-based placement scheme and a uniform compression scheme. It took our methods at most about 9 s to decide the overall solution for placement, compression, and data fusion at the design stage. This demonstrates the effectiveness and applicability of our unified statistical design methodology.

In 3D ICs, interlayer communication is achieved using through-silicon-vias (TSVs), which can suffer from cross coupling if placed naïvely. In this paper, cross coupling between TSVs is modeled, and a chip-scale TSV coupling mitigation scheme is presented using TSV shielding. A geometric coupling model is developed which is simple enough to quickly estimate the pairwise coupling between TSVs, unlike circuit models of coupling that have been proposed in previous works. Our geometric model's ability to make fast accurate estimations of chip-scale cross coupling make it a good model to use for shield placement optimization.

It is widely known that fabrication and thermal variations influence circuit delay. In three dimensional circuits (3D-ICs), due to the incorporation of through-silicon-vias (TSVs), thermal stress also becomes an increasing contributor to gate delay. As a result, thermal variations cause not only direct impact to the circuit parameters, they also cause 3D-IC stress variations resulting in an additional source of variability which needs to be accounted for in statistical static timing analysis (SSTA). In this paper, we study the impact (both direct and indirect - through thermal stress) of thermal variations on gate delay, and propose Monte Carlo (MC) simulation based fabrication, temperature and thermal stress variations aware SSTA methodology that accounts for this complex effect. We show that thermal stress variations cause extra -4~10% delay changes compared with the SSTA that only accounts for fabrication and direct thermal impacts, indicating that thermal stress should be considered together with direct temperature effect. We then develop a more efficient canonical thermal stress aware SSTA method that can achieve good accuracy and 843x speedup compared with MC based method.

The three dimensional circuit (3D-IC) brings forth new challenges to physical design such as allocation and management of through-silicon-vias (TSVs). Meanwhile, the thermal issues in 3D-IC becomes significant necessitating the use of active cooling schemes such as micro-channel liquid coolings. Both TSVs and micro-channels go through the interlayer regions of 3D-IC resulting in potential resource conflict. This paper investigates the co-optimization of TSV assignment to interlayer nets and micro-channel allocation such that both wirelength and micro-channel cooling energy are co-optimized. We propose a multi-commodity flow based formulation to solve the co-optimization. The experimental results show that, our approach achieves 51% cooling power savings or 6.08% wire length reduction compared with the approaches that assign TSVs and allocate micro-channels separately.

In this paper, we investigate dynamic thermal management (DTM) policies under soft thermal constraint that allow the thermal constraint to be violated occasionally for boosting system performance. First, we investigate soft-constraint DTM using lumped radio control (RC) thermal models. We develop analytical expressions for the optimal core frequency policies that maximize overall performance under soft thermal constraint for both single-core and homogeneous multicore processors. We then generalize the problem to heterogeneous multicore processor and use a more accurate distributed RC thermal model to account for the spatial thermal variation. The generalized problem also takes into account the impact of increased temperature on transistor delay and leakage power. The problem is solved by convex optimization. Experimental results indicate that for a two-core processor, a mere 10 °C increase in the core temperature for 100 s results in about 30% performance gain.

Micro-channel based liquid cooling has significant capability of removing high density heat in 3D-ICs. The conventional micro-channel structures investigated for cooling 3D-ICs use straight channels. However, the presence of TSVs which form obstacles to the micro-channels prevents distribution of straight micro-channels. In this paper, we investigate the methodology of designing TSV-constrained micro-channel infrastructure. Specifically, we decide the locations and geometry of micro-channels with bended structure so that the cooling effectiveness is maximized. Our micro-channel structure could achieve up to 87% pumping power savings compared with the structure using straight micro-channels.

In this paper, we investigate the gate sizing problem and develop techniques for improving the runtime by effectively exploiting the graphics processing unit (GPU) resources. Theoretically, we investigate a randomized cutting plane-based convex optimization technique which is highly parallelizable and can effectively exploit the single instruction multiple data structure imposed by GPUs. In order to further improve the runtime, we also develop GPU-oriented implementation guidelines that exploit the specific structure that convex gate sizing formulations impose. We implemented our method on NVIDIA Tesla 10 GPU and obtain 21× to 400× speedup compared to the MOSEK optimization tool implemented on conventional CPU. The quality of solution of our method is very close to that achieved by MOSEK, since both are optimal.

Micro-channel cooling shows great potential in removing high density heat in 3D circuits. The current micro-channel heat sink designs spread the entire surface to be cooled with micro-channels. This approach, though might provide sufficient cooling, requires quite high pumping power. In this paper, we investigate the non-uniform allocation of micro-channels to provide sufficient cooling with less pumping power. Specifically, we decide the count, location and pumping pressure drop/flow rate of micro-channels such that acceptable cooling is achieved at minimum pumping power. Thermal wake effect and runtime pressure drop/flow rate control are also considered. The experiments showed that, compared with the conventional design which spreads micro-channels all over the chip, our non-uniform microchannel design achieves 55--60% pumping power saving.

In this paper, we investigate Dynamic Thermal Management (DTM) policies under soft thermal constraint that allows the thermal constraint to be violated for a user specified period. For single core processor, we develop analytical expression for the optimal frequency policy under the soft constraint such that maximal performance can be extracted. We extend this problem to multi-core processor and provide optimal frequency policy when all cores run at same frequency. We also present LP based approximated formulation that generates frequency policies where each core has separate frequency control and considers leakage power. We use frequency legalization to approximate the frequency into discrete values. Experimental results indicate that 10 degree celsius increase in core temperature for 100sec results in 13% performance gain for single core processor, and 30% performance gain for two-core processor. Without Tmax constraint, the performance improves almost 100% for two-core processor.

Thermal/power issues have become increasingly important with more and more transistors being put on a single chip. Many dynamic thermal/power management techniques have been proposed to address such issues but they all heavily depend on accurate knowledge of the chip's thermal state during runtime. In this paper we describe a unified statistical framework for designing an on-chip thermal sensing infrastructure which can be used to track the chip's thermal state at runtime. Specifically we address the following problems: (1)sensor placement; (2)sensor data compression; (3)sensor data fusion; (4)overall interplay. Our methods exploit the thermal correlation to generate the overall solution in both the noiseless and noisy sensor settings. Our framework is also capable of choosing the appropriate degree of compression for each sensor while accounting for their local space constraints when doing the sensor deployment. The experimental results showed that our infrastructure can improve the temperature estimation accuracy by 27% (on average) as compared to an equivalent system that uses range-based placement and uniform compression. It took our methods about 6.3 seconds to decide the overall solution for placement, compression and data fusion at design stage. This demonstrates the effectiveness and applicability of our unified statistical design methodology.