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Martin T. Storma

dblp:77/2668 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1976
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Memory systems · 59% High-performance computing · 31% Storage systems · 9%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory management › memory allocation
dynamic memory allocation
0.011976
A Programmable Dynamic Memory Allocation System for Input/Output of Digital Data into Standard Computer Memories at 40 Megasamples/s · IEEE Trans. Computers 1976
High-performance computing › data transfer
high-speed data transfer
0.011976
A Programmable Dynamic Memory Allocation System for Input/Output of Digital Data into Standard Computer Memories at 40 Megasamples/s · IEEE Trans. Computers 1976
Memory systems
memory architecture
0.021976
A Real-Time Hardware System for Digital Processing of Wide-Band Video Images · IEEE Trans. Computers 1976
A Programmable Dynamic Memory Allocation System for Input/Output of Digital Data into Standard Computer Memories at 40 Megasamples/s · IEEE Trans. Computers 1976
Memory systems
magnetic core memory
0.011976
A Programmable Dynamic Memory Allocation System for Input/Output of Digital Data into Standard Computer Memories at 40 Megasamples/s · IEEE Trans. Computers 1976
Storage systems › flash and SSD
solid-state drive
0.011976
A Programmable Dynamic Memory Allocation System for Input/Output of Digital Data into Standard Computer Memories at 40 Megasamples/s · IEEE Trans. Computers 1976

Methods — techniques the papers use, named apart from their topics

microprogrammed control · 0.0digital-to-analog conversion · 0.0analog-to-digital conversion · 0.0
YearPublicationVenuePosition
1976 A Programmable Dynamic Memory Allocation System for Input/Output of Digital Data into Standard Computer Memories at 40 Megasamples/s
abstract
A memory control unit is described, which, operating in conjunction with a special purpose digital computer, achieves real-time storage into and retrieval from computer memory of individual video images undergoing on-line digitization, processing, and reconstitution. The memory control unit is capable of rapid sequential access on up to six 16 K-word core and two 131 K-word (28-bit word) solid-state memories, achieving data transfers to or from ememory at up to 40 million 9-bit samples/s for 33 ms. The memory control unit employs a variety of data rates, and can, under program control, assemble one or more bytes into, or disassemble one or more bytes from, each memory word. The control unit can sign extend incoming data to any of four different byte lengths from any of four different byte lengths. The control unit possesses dual data busses, one dedicated to memory read operations and a second capable of either "reads from" or "writes into" memory. The eight memory modules are sequenced by a small microprogrammed control store loadable from an associated computer.
Barry K. Gilbert, Martin T. Storma, Keith C. Ballard, Leon W. Hobrock, Carl E. James, Earl H. Wood
IEEE Trans. Computers2
1976 A Real-Time Hardware System for Digital Processing of Wide-Band Video Images
abstract
A high-fidelity video digitizer/processor extracts spatial and gray-scale information from high resolution dynamic video imagery. The 15-MHz bandwidth 60/s images(fields) are low pass filtered to minimize aliasing and digitized in real-time at 20 million samples pe second (MS/s), 9 bits/sample; sequential fields are transferred to memory, retrieved from memory after computer image processing, and reconstituted at up to 40 MS/s into 60 field/s video of 525, 875, or 1225 lines/frame (two interlaced fields). A/D and D/A converters are synchronized with memory by a high-speed interface, composed of a central data interchange (DI), and 8 rarially connected I/O ports. The DI connects the data paths of one or more ports, each communicating with one or more external devices. Separate 16-bit, 40 megawords/s, input and output data buses between each port and the DI allow data entry through any port to the DI and output from the DI through any port(s), even the same port from which the input originated. The A/D and D/A are served by a single port. Two other ports communicate with CDC 3500 and CDC 1700 computers. Yet another port controls up to two megawords of core/solid-state memory, of which 358K word may be accessed at the full data rate. Storage rates into existing memory of 40 MS/s are achieved for 16-32 ms.
Barry K. Gilbert, Martin T. Storma, Carl E. James, Leon W. Hobrock, Edward S. Yang, Keith C. Ballard, Earl H. Wood
IEEE Trans. Computers2